cont2060.vhd

学EDA 的时候做的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cont2060 IS
    PORT (CLK,RST,EN,SEL: IN STD_LOGIC;                     
          CQ :BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);
          CQL,CQH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);   
          COUT:OUT STD_LOGIC );
    END cont2060;
ARCHITECTURE behav OF cont2060 IS
  SIGNAL CQI: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL  NUM  : STD_LOGIC_VECTOR(7 DOWNTO 0); 
  BEGIN
 PROCESS  (CLK, RST, EN,SEL)   
   BEGIN
   IF SEL='1'THEN NUM<="00010011";
      ELSE NUM<="00111011";
    END IF;
      IF RST = '1' THEN   CQI <= (OTHERS =>'0') ;  
       ELSIF CLK'EVENT AND CLK='1' THEN        
        IF EN = '1' THEN                      
          IF CQI < NUM THEN   CQI <= CQI + 1;  
            ELSE    CQI <= (OTHERS =>'0'); 
          END IF;
        END IF;
     END IF;
   IF CQI=NUM THEN COUT <='1';
   ELSE COUT<='0';
   END IF;
 END PROCESS ;
  WITH CQI SELECT
 CQ <=CQI    WHEN "00000000"TO"00001001",
    CQI+6    WHEN "00001010"TO"00010011",
    CQI+12   WHEN "00010100"TO"00011101",
    CQI+18   WHEN "00011110"TO"00100111",
    CQI+24   WHEN "00101000"TO"00110001",
    CQI+30   WHEN "00110010"TO"00111011",
    CQI  WHEN  OTHERS;
    CQL<=CQ(3 DOWNTO 0);
    CQH<=CQ(7 DOWNTO 4);
 END behav;