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<TITLE>80x86 Integer Instruction Set (8088 - Pentium)</TITLE>
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<H1>80x86 Integer Instruction Set (8088 - Pentium)</H1>
<P>Click <A HREF="fpuopcode.html">FPU opcodes </A>for floating point instructions</P>
<P><A HREF="opcode.html#end of legend">Jump</A> to end of legend</P>
<H2>Legend:</H2>
<PRE><B><FONT SIZE=+1> General
</FONT> acc </B> = AL, AX or EAX unless specified otherwise
<B> reg </B> = any general register
<B> r8 </B> = any 8-bit register
<B>r16 </B> = any general purpose 16-bit register
<B> r32</B> = any general purpose 32-bit register
<B> imm</B> = immediate data
<B> imm8 </B> = 8-bit immediate data
<B>imm16</B> = 16-bit immediate data
<B> mem</B> = memory address
<B>mem8</B> = address of 8-bit data item
<B>mem16</B> = address of 16-bit data item
<B>mem32</B> = address of 32-bit data item
<B>mem48</B> = address of 48-bit data item
<B>dest</B> = 16/32-bit destination
<B>short</B> = 8-bit destination
<B><FONT SIZE=+1>Integer instruction timings:
</FONT></B> <B>n</B> - generally refers to a number of repeated counts
<B>m</B> - in a jump or call;
286: bytes in next instruction
386/486: number of components
(each byte of opcode) + 1 (if immed data) + 1 (if displacement)
<B>EA</B> = cycles to calculate the Effective Address
8088/8086:
base = 5 BP+DI or BX+SI = 7 BP+DI+disp or BX+SI+disp = 11
index = 5 BX+DI or BP+SI = 8 BX+DI+disp or BP+SI+disp = 12
disp = 6 segment override = +2
286 - 486:
base+index+disp = +1 all others, no penalty
instruction length:
The byte count includes the opcode length and length of any required
displacement or immediate data. If the displacement is optional, it
is shown as d() with the possible lengths in parentheses. If the
immediate data is optional, it is shown as i() with the possible
lengths in parentheses.
<B><FONT SIZE=+1>pairing categories for Pentium:
</FONT></B> <B> NP</B> = not pairable
<B>UV</B> = pairable in the U pipe or V pipe
<B>PU</B> = pairable in the U pipe only
<B>PV</B> = pairable in the V pipe only</PRE>
<P><A NAME="end of legend"></A>(end of legend)</P>
<H3>Instruction formats, clock cycles and Pentium® Pairing info</H3>
<PRE><B>AAA</B> ASCII adjust after addition
bytes 8088 186 286 386 486 Pentium
1 8 8 3 4 3 3 NP
Example: aaa
<B>AAD</B> ASCII adjust AX before division (second byte is divisor)
bytes 8088 186 286 386 486 Pentium
2 60 15 14 19 14 10 NP
Example: aad
<B>AAM</B> ASCII adjust AX after multiply (second byte is divisor)
bytes 8088 186 286 386 486 Pentium
2 83 19 16 17 15 18 NP
Example: aam
<B>AAS</B> ASCII adjust AL after subtraction
bytes 8088 186 286 386 486 Pentium
1 8 7 3 4 3 3 NP
Example: aas
<B>ADC</B> Integer add with carry
operands bytes 8088 186 286 386 486 Pentium
reg, reg 2 3 3 2 2 1 1 PU
mem, reg 2+d(0,2) 24+EA 10 7 7 3 3 PU
reg, mem 2+d(0,2) 13+EA 10 7 6 2 2 PU
reg, imm 2+i(1,2) 4 4 3 2 1 1 PU
mem, imm 2+d(0,2) 23+EA 16 7 7 3 3 PU*
+i(1,2)
acc, imm 1+i(1,2) 4 4 3 2 1 1 PU
* = not pairable if there is a displacement and immediate
Example: adc eax, ebx
<B>ADD</B> Integer addition
operands bytes 8088 186 286 386 486 Pentium
reg, reg 2 3 3 2 2 1 1 UV
mem, reg 2+d(0,2) 24+EA 10 7 7 3 3 UV
reg, mem 2+d(0,2) 13+EA 10 7 6 2 2 UV
reg, imm 2+i(1,2) 4 4 3 2 1 1 UV
mem, imm 2+d(0,2) 23+EA 16 7 7 3 3 UV*
+i(1,2)
acc, imm 1+i(1,2) 4 4 3 2 1 1 UV
* = not pairable if there is a displacement and immediate
Example: add eax, ebx
<B>AND</B> Logical AND
operands bytes 8088 186 286 386 486 Pentium
reg, reg 2 3 3 2 2 1 1 UV
mem, reg 2+d(0,2) 24+EA 10 7 7 3 3 UV
reg, mem 2+d(0,2) 13+EA 10 7 6 2 2 UV
reg, imm 2+i(1,2) 4 4 3 2 1 1 UV
mem, imm 2+d(0,2) 23+EA 16 7 7 3 3 UV*
+i(1,2)
acc, imm 1+i(1,2) 4 4 3 2 1 1 UV
* = not pairable if there is a displacement and immediate
Example: and eax, ebx
<B>ARPL</B> Adjust RPL field of selector (286+)
operands bytes 286 386 486 Pentium
reg, reg 2 10 20 9 7 NP
mem, reg 2+d(0-2) 11 21 9 7 NP
Example: arpl ax, bx
<B>BOUND</B> Check array index against bounds (186+)
operands bytes 186 286 386 486 Pentium
reg, mem 4 35 13 10 7 8 NP
Example: bound bx, array
<B>BSF</B> Bit scan forward (386+)
operands bytes 386 486 Pentium
r16, r16 3 10+3n 6-42 6-34 NP
r32, r32 3 10+3n 6-42 6-42 NP
r16, m16 3+d(0,1,2) 10+3n 7-43 6-35 NP
r32, m32 3+d(0,1,2,4) 10+3n 7-43 6-43 NP
Example: bsf eax, [esi]
<B>BSR</B> Bit scan reverse (386+)
operands bytes 386 486 Pentium
r16, r16 3 10+3n 6-103 7-39 NP
r32, r32 3 10+3n 7-104 7-71 NP
r16, m16 3+d(0,1,2) 10+3n 6-103 7-40 NP
r32, m32 3+d(0,1,2,4) 10+3n 7-104 7-72 NP
Example: bsr eax, [esi]
<B>BSWAP</B> Byte swap (486+)
operand bytes 486 Pentium
r32 2 1 1 NP
Example: bswap eax
<B>BT</B> Bit test (386+)
operands bytes 386 486 Pentium
reg, reg 3 3 3 4 NP
mem, reg 3+d(0,1,2,4) 12 8 9 NP
reg, imm8 3+i(1) 3 3 4 NP
mem, imm8 3+d(0,1,2,4)+i(1) 6 3 4 NP
Example: bt eax, 4
<B>BTC</B> Bit test and complement (386+)
operands bytes 386 486 Pentium
reg, reg 3 6 6 7 NP
mem, reg 3+d(0,1,2,4) 13 13 13 NP
reg, imm8 3+i(1) 6 6 7 NP
mem, imm8 3+d(0,1,2,4)+i(1) 8 8 8 NP
Example: btc eax, 4
<B>BTR</B> Bit test and reset (386+)
operands bytes 386 486 Pentium
reg, reg 3 6 6 7 NP
mem, reg 3+d(0,1,2,4) 13 13 13 NP
reg, imm8 3+i(1) 6 6 7 NP
mem, imm8 3+d(0,1,2,4)+i(1) 8 8 8 NP
Example: btr eax, 4
<B>BTS</B> Bit test and set (386+)
operands bytes 386 486 Pentium
reg, reg 3 6 6 7 NP
mem, reg 3+d(0,1,2,4) 13 13 13 NP
reg, imm8 3+i(1) 6 6 7 NP
mem, imm8 3+d(0,1,2,4)+i(1) 8 8 8 NP
Example: bts eax, 4
<B>CALL</B> Call subroutine
operand bytes 8088 186 286 386 486 Pentium
near 3 23 14 7+m 7+m 3 1 PV
reg 2 20 13 7+m 7+m 5 2 NP
mem16 2+d(0-2) 29+EA 19 11+m 10+m 5 2 NP
far 5 36 23 13+m 17+m 18 4 NP
mem32 2+d(0-2) 53+EA 38 16+m 22+m 17 4 NP
Protected Mode
operand bytes 286 386 486 Pentium
far 5 26+m 34+m 20 4-13 NP
mem32 2+d(0-2) 29+m 38+m 20 5-14 NP
cycles not shown for calls through call and task gates
Example: call my_function
<B>CBW</B> Convert byte to word (AL --> AX)
bytes 8088 186 286 386 486 Pentium
1 2 2 2 3 3 3 NP
Example: cbw
<B>CWDE</B> Convert word to dword (386+) (AX --> EAX)
bytes 386 486 Pentium
1 3 3 3 NP
Example: cwde
<B>CWD</B> Convert word to double (AX --> DX:AX)
bytes 8088 186 286 386 486 Pentium
1 5 4 2 2 3 2 NP
Example: cwd
<B>CDQ</B> Convert double to quad (EAX --> EDX:EAX)
bytes 386 486 Pentium
1 2 3 2 NP
Example: cdq
<B>CLC</B> Clear the carry flag
bytes 8088 186 286 386 486 Pentium
1 2 2 2 2 2 2 NP
Example: clc
<B>CLD</B> Clear the direction flag (set to forward direction)
bytes 8088 186 286 386 486 Pentium
1 2 2 2 2 2 2 NP
Example: cld
<B>CLI</B> Clear the interrupt flag (disable interrupts)
bytes 8088 186 286 386 486 Pentium
1 2 2 3 3 5 7 NP
Example: cli
<B>CLTS</B> Clear task switched flag in CR0 (286+)
bytes 286 386 486 Pentium
2 2 5 7 10 NP
Example: clts
<B>CMC</B> Complement carry flag
bytes 8088 186 286 386 486 Pentium
1 2 2 2 2 2 2 NP
Example: cmc
<B>CMP</B> Compare two operands
operands bytes 8088 186 286 386 486 Pentium
reg, reg 2 3 3 2 2 1 1 UV
mem, reg 2+d(0,2) 13+EA 10 7 5 2 2 UV
reg, mem 2+d(0,2) 13+EA 10 6 6 2 2 UV
reg, imm 2+i(1,2) 4 4 3 2 1 1 UV
mem, imm 2+d(0,2) 14+EA 10 6 5 2 2 UV*
+i(1,2)
acc, imm 1+i(1,2) 4 4 3 2 1 1 UV
* = not pairable if there is a displacement and immediate
Example: cmp eax, 3
<B>CMPS/CMPSB/CMPSW/CMPSD</B> Compare string operands
variations bytes 8088 186 286 386 486 Pentium
cmpsb 1 30 22 8 10 8 5 NP
cmpsw 1 - - - 10 8 5 NP
cmpsd 1 - - - 10 8 5 NP
repX cmpsb 2 9+30n 5+22n 5+9n 5+9n 7+7n* 9+4n NP
repX cmpsw 2 9+30n 5+22n 5+9n 5+9n 7+7n* 9+4n NP
repX cmpsd 2 - - - 5+9n 7+7n* 9+4n NP
repX = repe, repz, repne or repnz
* : 5 if n = 0
Example: repne cmpsb
<B>CMPXCHG</B> Compare and Exchange (486+)
operands bytes 486 Pentium
reg, reg 3 6 5 NP
mem, reg 3+d(0-2) 7-10 6 NP
Example: cmpxchg ebx, edx
<B>CMPXCHG8B</B> Compare and Exchange 8 bytes (Pentium+)
operands bytes Pentium
mem, reg 3+d(0-2) 10 NP
Example: cmpxchg8b [ebx], edx
<B>CPUID</B> CPU identification (Pentium+)
bytes Pentium
2 14 NP
Example: cpuid
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