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<TITLE> 80x86 Opcodes </TITLE>
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<BODY BGCOLOR="#FFFFFF">
<center><h2>80x86 Opcodes</h2></center>
<HR>
Here is a list of instructions and opcodes used by
Intel, AMD, Cyrix and Nexgen. <I> Gdb </I> was used get all the
info out of the processors. This page was made by
<A HREF="http://www.imada.ou.dk/~alv/">Asbjørn Leth Vonsild</A>
(<A HREF="mailto:alv@imada.ou.dk">alv@imada.ou.dk</A>)
and <A HREF="http://www.imada.ou.dk/~jews/">Jesper Pedersen</A>
(<A HREF="mailto:jews@imada.ou.dk">jews@imada.ou.dk</A>).
Please send any comments, questions directly to the original authors. <BR>
Last updated : 03.10.1996 at 11:30:00 <BR>
<HR>
<H2> Table of contents </H2>
<UL>
<LI> <A HREF="#Technical"> Technical Specifications </A> <BR>
<LI> <A HREF="#Instruction"> Instructions and Opcodes </A> <BR>
<UL>
<LI> <A HREF="#Main"> Main instructions </A> <BR>
<LI> <A HREF="#Co"> Co-Processor instructions </A> <BR>
<LI> <A HREF="#Cond"> Condition Codes </A> <BR>
<LI> <A HREF="#FpuCond"> Condition Codes for FCMOVcc </A> <BR>
</UL>
<LI> <A HREF="#Futher"> Further Reading </A> <BR>
</UL>
<A NAME="Technical"> <HR> </A>
<H2>Technical Specifications</H2>
<TABLE BORDER>
<TR><TH></TH>
<TH>Introduction<BR>
Date</TH>
<TH>Clock Speeds</TH>
<TH>Bus Width</TH>
<TH>Number of<BR>
Transistors</TH>
<TH>Addressable<BR>
Memory</TH>
<TH>Virtual<BR>
Memory</TH>
<TH>Brief<BR>
Description</TH></TR>
<TR>
<TD ALIGN=CENTER><B>4004</B><TD ALIGN=CENTER>11/15/71</TD><TD ALIGN=CENTER>108 KHz</TD><TD ALIGN=CENTER>4 bits</TD><TD ALIGN=CENTER>2,300<BR>(10 microns)</TD><TD ALIGN=CENTER>640 bytes</TD><TD><BR></TD><TD ALIGN=CENTER>First microcomputer chip,<BR>Arithmetic manipulation</TD></TR>
<TR>
<TD ALIGN=CENTER><B>8008</B></TD>
<TD ALIGN=CENTER>4/1/72</TD><TD ALIGN=CENTER>108 KHz</TD><TD ALIGN=CENTER>8 bits</TD><TD ALIGN=CENTER>3,500</TD><TD ALIGN=CENTER>16 KBytes</TD><TD ALIGN=CENTER><BR></TD><TD ALIGN=CENTER>Data/character manipulation</TD></TR>
<TR>
<TD ALIGN=CENTER><B>8080</B></TD>
<TD ALIGN=CENTER>4/1/74</TD><TD ALIGN=CENTER>2 MHz</TD><TD ALIGN=CENTER>8 bits</TD><TD ALIGN=CENTER>6,000<BR>(6 microns)</TD><TD ALIGN=CENTER>64 KBytes</TD><TD ALIGN=CENTER><BR>
</TD><TD ALIGN=CENTER>10X the performance of the 8008</TD></TR>
<TR>
<TD ALIGN=CENTER><B>8086</B></TD>
<TD ALIGN=CENTER>6/8/78</TD>
<TD ALIGN=CENTER>5 MHz<BR> 8 MHz<BR> 10 MHz</TD><TD ALIGN=CENTER>16 bits</TD><TD ALIGN=CENTER>29,000<BR>(3 microns)</TD><TD ALIGN=CENTER>1 Megabyte</TD>
<TD><BR></TD><TD ALIGN=CENTER>10X the performance of the 8080</TD></TR>
<TR>
<TD ALIGN=CENTER><B>8088</B></TD>
<TD ALIGN=CENTER>6/1/79</TD><TD ALIGN=CENTER>5 MHz<BR> 8 MHz</TD><TD ALIGN=CENTER>8 bits</TD><TD ALIGN=CENTER>29,000<BR>(3 microns)</TD><TD ALIGN=CENTER><BR></TD><TD ALIGN=CENTER><BR></TD><TD ALIGN=CENTER>Identical to 8086 except for its 8-bit external bus</TD></TR>
<TR>
<TD ALIGN=CENTER><B>80286</B></TD>
<TD ALIGN=CENTER>2/1/82</TD><TD ALIGN=CENTER>8 MHz<BR> 10 MHz<BR> 12 MHz</TD><TD ALIGN=CENTER>16 bits</TD><TD ALIGN=CENTER>134,000<BR>(1.5 microns)</TD><TD ALIGN=CENTER>16 Megabytes</TD><TD ALIGN=CENTER>1 gigabyte</TD><TD ALIGN=CENTER>3-6X the performance of the 8086</TD></TR>
<TR>
<TD ALIGN=CENTER><B>Intel386<FONT SIZE=2>(TM)</FONT>DX Microprocessor</B></TD>
<TD ALIGN=CENTER>10/17/85</TD><TD ALIGN=CENTER>16 MHz<BR>20 MHz<BR>25 MHz<BR>33 MHz</TD><TD ALIGN=CENTER>32 bits</TD><TD ALIGN=CENTER>275,000<BR>(1 micron)</TD><TD ALIGN=CENTER>4 gigabytes</TD><TD ALIGN=CENTER>64 terabytes
</TD><TD ALIGN=CENTER>First X86 chip to handle 32-bit data sets<BR></TD></TR>
<TR>
<TD ALIGN=CENTER><B>Intel386<FONT SIZE=2>(TM)</FONT>SX Microprocessor</TD>
<TD ALIGN=CENTER>6/16/88</TD><TD ALIGN=CENTER>16 MHz<BR>20 MHz</TD><TD ALIGN=CENTER>16 bits</TD><TD ALIGN=CENTER>275,000<BR>(1 micron)</TD><TD ALIGN=CENTER>4 gigabytes</TD><TD ALIGN=CENTER>64 terabytes</TD><TD ALIGN=CENTER>16-bit address bus enabled low-cost 32-bit processing
<BR></TD></TR>
<TR>
<TD ALIGN=CENTER><B>Intel486<FONT SIZE=2>(TM)</FONT>DX Microprocessor</B></TD>
<TD ALIGN=CENTER>4/10/89</TD><TD ALIGN=CENTER>25 MHz<BR>33 MHz<BR>50 MHz</TD><TD ALIGN=CENTER>32 bits</TD><TD ALIGN=CENTER>1,200,000<BR>(1 micron, .8 micron with 50 MHz)</TD><TD ALIGN=CENTER>4 gigabytes</TD><TD ALIGN=CENTER>64 terabytes</TD><TD ALIGN=CENTER>Level 1 cache on chip
<BR></TD></TR>
<TR>
<TD ALIGN=CENTER><B>Intel486<FONT SIZE=2>(TM)</FONT>SX Microprocessor</B></TD>
<TD ALIGN=CENTER>4/22/91</TD><TD ALIGN=CENTER>16 MHz<BR>20 MHz<BR>25 MHz<BR>33 MHz</TD><TD ALIGN=CENTER>32 bits</TD><TD ALIGN=CENTER>1,185,000<BR>(.8 micron)</TD><TD ALIGN=CENTER>4 gigabytes</TD><TD ALIGN=CENTER>64 terabytes</TD><TD ALIGN=CENTER>identical in design to Intel486(TM) DX but without math coprocessor<BR></TD></TR>
<TR>
<TD ALIGN=CENTER><B>Pentium® Processor</B></TD>
<TD ALIGN=CENTER>3/22/93</TD><TD ALIGN=CENTER>60MHz<BR>66MHz<BR>75MHz<BR>90MHz<BR>100MHz<BR>120MHz<BR>133MHz<BR>150MHz<BR>166MHz</TD><TD ALIGN=CENTER>32 bits</TD><TD ALIGN=CENTER>3.1 million<BR>(.8 micron)</TD><TD ALIGN=CENTER>4 gigabytes</TD><TD ALIGN=CENTER>64 terabytes</TD><TD ALIGN=CENTER>superscaler architecture brought 5X the performance of the 33-MHz Intel486 DX
processor<BR></TD></TR>
<TR>
<TD ALIGN=CENTER><B>Pentium® Pro Processor</B></TD>
<TD ALIGN=CENTER>3/27/95</TD><TD ALIGN=CENTER>150MHz<BR>180MHz<BR>200MHz</TD><TD ALIGN=CENTER>32 bits</TD><TD ALIGN=CENTER>5.5 million<BR>(.32 micron)</TD><TD ALIGN=CENTER>4 gigabytes</TD><TD ALIGN=CENTER>64 terabytes</TD><TD ALIGN=CENTER>dynamic execution architecture drives high-performing processor
<BR></TD></TR>
</TABLE>
</CENTER>
<P><br>
<A NAME="Instruction"> <HR> </A>
<H2> Instructions and opcodes </H2>
<P>
<STRONG> oo : Function </STRONG> <BR>
<UL>
<LI> 00 : If mmm = 110, then a displacement follows the operation; otherwise, no displacement is used <BR>
<LI> 01 : An 8-bit signed displacement follows the opcode <BR>
<LI> 10 : A 16-bit signed displacement follows the opcode <BR>
<LI> 11 : mmm specifies a register, instead of an addressing mode <BR>
</UL>
<STRONG> mmm : Function </STRONG> <BR>
<UL>
<LI> 000 : DS:[BX+SI] <BR>
<LI> 001 : DS:[BX+DI] <BR>
<LI> 010 : SS:[BP+SI] <BR>
<LI> 011 : SS:[BP+DI] <BR>
<LI> 100 : DS:[SI] <BR>
<LI> 101 : DS:[DI] <BR>
<LI> 110 : SS:[BP] <BR>
<LI> 111 : DS:[BX] <BR>
</UL>
<STRONG> rrr : W=0 : W=1 : reg32 </STRONG> <BR>
<UL>
<LI> 000 : AL : AX : EAX <BR>
<LI> 001 : CL : CX : ECX <BR>
<LI> 010 : DL : DX : EDX <BR>
<LI> 011 : BL : BX : EBX <BR>
<LI> 100 : AH : SP : ESP <BR>
<LI> 101 : CH : BP : EBP <BR>
<LI> 110 : DH : SI : ESI <BR>
<LI> 111 : BH : DI : EDI <BR>
</UL>
<STRONG> sss : Segment Register </STRONG> <BR>
<UL>
<LI> 000 : ES <BR>
<LI> 001 : CS <BR>
<LI> 010 : SS <BR>
<LI> 011 : DS <BR>
<LI> 100 : FS (Only 386+)
<LI> 101 : GS (Only 386+)
</UL>
<STRONG> rrr : Index Register </STRONG <BR>
<UL>
<LI> 000 : EAX <BR>
<LI> 001 : ECX <BR>
<LI> 010 : EDX <BR>
<LI> 011 : EBX <BR>
<LI> 100 : No Index <BR>
<LI> 101 : EBP <BR>
<LI> 110 : ESI <BR>
<LI> 111 : EDI <BR>
</UL>
<STRONG> 32 bit addressing-mode </STRONG> <BR>
<TABLE BORDER=all CELLSPACING=1 CELLPADDING=4 COLS=5 WIDTH=100%>
<COLW COL=2-5 WIDTH=3>
<HSPEC COL=1 ALIGN=char CHAR="-">
<TR>
<TH>oo
<TH>mmm
<TH>rrr
<TH>Description
<TR>
<TD>00
<TD>000
<TD>
<TD>DS:[EAX]
<TR>
<TD>00
<TD>001
<TD>
<TD>DS:[ECX]
<TR>
<TD>00
<TD>010
<TD>
<TD>DS:[EDX]
<TR>
<TD>00
<TD>011
<TD>
<TD>DS:[EBX]
<TR>
<TD>00
<TD>100
<TD>000
<TD>DS:[EAX+scaled_index]
<TR>
<TD>00
<TD>100
<TD>001
<TD>DS:[ECX+scaled_index]
<TR>
<TD>00
<TD>100
<TD>010
<TD>DS:[EDX+scaled_index]
<TR>
<TD>00
<TD>100
<TD>011
<TD>DS:[EBX+scaled_index]
<TR>
<TD>00
<TD>100
<TD>100
<TD>SS:[ESP+scaled_index]
<TR>
<TD>00
<TD>100
<TD>101
<TD>DS:[disp32+scaled_index]
<TR>
<TD>00
<TD>100
<TD>110
<TD>DS:[ESI+scaled_index]
<TR>
<TD>00
<TD>100
<TD>111
<TD>DS:[EDI+scaled_index]
<TR>
<TD>00
<TD>101
<TD>
<TD>DS:disp32
<TR>
<TD>00
<TD>110
<TD>
<TD>DS:[ESI]
<TR>
<TD>00
<TD>111
<TD>
<TD>DS:[EDI]
<TR>
<TD>01
<TD>000
<TD>
<TD>DS:[EAX+disp8]
<TR>
<TD>01
<TD>001
<TD>
<TD>DS:[ECX+disp8]
<TR>
<TD>01
<TD>010
<TD>
<TD>DS:[EDX+disp8]
<TR>
<TD>01
<TD>011
<TD>
<TD>DS:[EBX+disp8]
<TR>
<TD>01
<TD>100
<TD>000
<TD>DS:[EAX+scaled_index+disp8]
<TR>
<TD>01
<TD>100
<TD>001
<TD>DS:[ECX+scaled_index+disp8]
<TR>
<TD>01
<TD>100
<TD>010
<TD>DS:[EDX+scaled_index+disp8]
<TR>
<TD>01
<TD>100
<TD>011
<TD>DS:[EBX+scaled_index+disp8]
<TR>
<TD>01
<TD>100
<TD>100
<TD>SS:[ESP+scaled_index+disp8]
<TR>
<TD>01
<TD>100
<TD>101
<TD>SS:[EBP+scaled_index+disp8]
<TR>
<TD>01
<TD>100
<TD>110
<TD>DS:[ESI+scaled_index+disp8]
<TR>
<TD>01
<TD>100
<TD>111
<TD>DS:[EDI+scaled_index+disp8]
<TR>
<TD>01
<TD>101
<TD>
<TD>SS:[EBP+disp8]
<TR>
<TD>01
<TD>110
<TD>
<TD>DS:[ESI+disp8]
<TR>
<TD>01
<TD>111
<TD>
<TD>DS:[EDI+disp8]
<TR>
<TD>10
<TD>000
<TD>
<TD>DS:[EAX+disp32]
<TR>
<TD>10
<TD>001
<TD>
<TD>DS:[ECX+disp32]
<TR>
<TD>10
<TD>010
<TD>
<TD>DS:[EDX+disp32]
<TR>
<TD>10
<TD>011
<TD>
<TD>DS:[EBX+disp32]
<TR>
<TD>10
<TD>100
<TD>000
<TD>DS:[EAX+scaled_index+disp32]
<TR>
<TD>10
<TD>100
<TD>001
<TD>DS:[ECX+scaled_index+disp32]
<TR>
<TD>10
<TD>100
<TD>010
<TD>DS:[EDX+scaled_index+disp32]
<TR>
<TD>10
<TD>100
<TD>011
<TD>DS:[EBX+scaled_index+disp32]
<TR>
<TD>10
<TD>100
<TD>100
<TD>SS:[ESP+scaled_index+disp32]
<TR>
<TD>10
<TD>100
<TD>101
<TD>SS:[EBP+scaled_index+disp32]
<TR>
<TD>10
<TD>100
<TD>110
<TD>DS:[ESI+scaled_index+disp32]
<TR>
<TD>10
<TD>100
<TD>111
<TD>DS:[EDI+scaled_index+disp32]
<TR>
<TD>10
<TD>101
<TD>
<TD>SS:[EBP+disp32]
<TR>
<TD>10
<TD>110
<TD>
<TD>DS:[ESI+disp32]
<TR>
<TD>10
<TD>111
<TD>
<TD>DS:[EDI+disp32]
</TABLE>
<BR>
<P>
<A NAME="Main"> <HR> </A>
<H3> Main Instructions </H3> <BR>
<BR>
<A HREF="#HA">A</A> ||
<A HREF="#HB">B</A> ||
<A HREF="#HC">C</A> ||
<A HREF="#HD">D</A> ||
<A HREF="#HE">E</A> ||
<A HREF="#HH">H</A> ||
<A HREF="#HI">I</A> ||
<A HREF="#HJ">J</A> ||
<A HREF="#HL">L</A> ||
<A HREF="#HM">M</A> ||
<A HREF="#HN">N</A> ||
<A HREF="#HO">O</A> ||
<A HREF="#HP">P</A> ||
<A HREF="#HR">R</A> ||
<A HREF="#HS">S</A> ||
<A HREF="#HT">T</A> ||
<A HREF="#HV">V</A> ||
<A HREF="#HW">W</A> ||
<A HREF="#HX">X</A><BR>
<P>
<TABLE BORDER=all CELLSPACING=1 CELLPADDING=4 COLS=5 WIDTH=100%>
<COLW COL=2-5 WIDTH=3>
<HSPEC COL=1 ALIGN=char CHAR="-">
<TR>
<TH>Name
<TH>Regs
<TH>Opcode
<TH>Proc
<TH>Description
<TR>
<TD><A NAME="HA">AAA</A>
<TD>
<TD>00110111
<TD>8086
<TD>ASCII Adjust After Addition
<TR>
<TD>AAD
<TD>Imm8
<TD>11010101
<TD>Pentium
<TD>ASCII Adjust Register AX Before Division
<TR>
<TD>
<TD>
<TD>1101010100001010
<TD>8086
<TD>ASCII Adjust Register AX Before Division
<TR>
<TD>AAM
<TD>Imm8
<TD>11010100
<TD>Pentium
<TD>ASCII Adjust AX Register After Multiplication
<TR>
<TD>
<TD>
<TD>1101010000001010
<TD>8086
<TD>ASCII Adjust AX Register After Multiplication
<TR>
<TD>AAS
<TD>
<TD>00111111
<TD>8086
<TD>ASCII Adjust AL Register After Substraction
<TR>
<TD>ADC
<TD>Reg,Reg
<TD>0001001woorrrmmm
<TD>8086
<TD>Add Integers with Carry
<TR>
<TD>
<TD>Mem,Reg
<TD>0001000woorrrmmm
<TD>8086
<TD>Add Integers with Carry
<TR>
<TD>
<TD>Reg,Mem
<TD>0001001woorrrmmm
<TD>8086
<TD>Add Integers with Carry
<TR>
<TD>
<TD>Acc,Imm
<TD>0001010w
<TD>8086
<TD>Add Integers with Carry
<TR>
<TD>
<TD>Reg,Imm8
<TD>1000001woo010mmm
<TD>8086
<TD>Add Integers with Carry
<TR>
<TD>
<TD>Mem,Imm8
<TD>1000001woo010mmm
<TD>8086
<TD>Add Integers with Carry
<TR>
<TD>
<TD>Reg,Imm
<TD>1000000woo010mmm
<TD>8086
<TD>Add Integers with Carry
<TR>
<TD>
<TD>Mem,Imm
<TD>1000000woo010mmm
<TD>8086
<TD>Add Integers with Carry
<TR>
<TD>ADD
<TD>Reg,Reg
<TD>0000001woorrrmmm
<TD>8086
<TD>Add Integers
<TR>
<TD>
<TD>Mem,Reg
<TD>0000000woorrrmmm
<TD>8086
<TD>Add Integers
<TR>
<TD>
<TD>Reg,Mem
<TD>0000001woorrrmmm
<TD>8086
<TD>Add Integers
<TR>
<TD>
<TD>Acc,Imm
<TD>0000010w
<TD>8086
<TD>Add Integers
<TR>
<TD>
<TD>Reg,Imm8
<TD>1000001woo000mmm
<TD>8086
<TD>Add Integers
<TR>
<TD>
<TD>Mem,Imm8
<TD>1000001woo000mmm
<TD>8086
<TD>Add Integers
<TR>
<TD>
<TD>Reg,Imm
<TD>1000000woo000mmm
<TD>8086
<TD>Add Integers
<TR>
<TD>
<TD>Mem,Imm
<TD>1000000woo000mmm
<TD>8086
<TD>Add Integers
<TR>
<TD>AND
<TD>Reg,Reg
<TD>0010001woorrrmmm
<TD>8086
<TD>Logical AND
<TR>
<TD>
<TD>Mem,Reg
<TD>0010000woorrrmmm
<TD>8086
<TD>Logical AND
<TR>
<TD>
<TD>Reg,Mem
<TD>0010001woorrrmmm
<TD>8086
<TD>Logical AND
<TR>
<TD>
<TD>Acc,Imm
<TD>0010010w
<TD>8086
<TD>Logical AND
<TR>
<TD>
<TD>Reg,Imm8
<TD>1000001woo100mmm
<TD>8086
<TD>Logical AND
<TR>
<TD>
<TD>Mem,Imm8
<TD>1000001woo100mmm
<TD>8086
<TD>Logical AND
<TR>
<TD>
<TD>Reg,Imm
<TD>1000000woo100mmm
<TD>8086
<TD>Logical AND
<TR>
<TD>
<TD>Mem,Imm
<TD>1000000woo100mmm
<TD>8086
<TD>Logical AND
<TR>
<TD>ARPL
<TD>Reg16,Reg16
<TD>01100011oorrrmmm
<TD>80286
<TD>Adjust Requester Privilege Level of Selector
<TR>
<TD>
<TD>Mem16,Reg16
<TD>01100011oorrrmmm
<TD>80286
<TD>Adjust Requester Privilege Level of Selector
<TR>
<TD><A NAME="HB">BOUND</A>
<TD>Reg16,Mem32
<TD>01100010oorrrmmm
<TD>80186
<TD>Check Array Index Against Bounds
<TR>
<TD>
<TD>Reg32,Mem64
<TD>01100010oorrrmmm
<TD>80386
<TD>Check Array Index Against Bounds
<TR>
<TD>BSF
<TD>RegWord,RegWord
<TD>0000111110111100oorrrmmm
<TD>80386
<TD>Bit Scan Forward
<TR>
<TD>
<TD>RegWord,MemWord
<TD>0000111110111100oorrrmmm
<TD>80386
<TD>Bit Scan Forward
<TR>
<TD>BSR
<TD>RegWord,RegWord
<TD>0000111110111101oorrrmmm
<TD>80386
<TD>Bit Scan Reverse
<TR>
<TD>
<TD>RegWord,MemWord
<TD>0000111110111101oorrrmmm
<TD>80386
<TD>Bit Scan Reverse
<TR>
<TD>BSWAP
<TD>RegWord
<TD>0000111111001rrr
<TD>80486
<TD>Byte swap
<TR>
<TD>BT
<TD>RegWord,Imm8
<TD>0000111110111010oo100mmm
<TD>80386
<TD>Bit Test
<TR>
<TD>
<TD>MemWord,Imm8
<TD>0000111110111010oo100mmm
<TD>80386
<TD>Bit Test
<TR>
<TD>
<TD>RegWord,RegWord
<TD>0000111110100011oorrrmmm
<TD>80386
<TD>Bit Test
<TR>
<TD>
<TD>MemWord,RegWord
<TD>0000111110100011oorrrmmm
<TD>80386
<TD>Bit Test
<TR>
<TD>BTC
<TD>RegWord,Imm8
<TD>0000111110111010oo111mmm
<TD>80386
<TD>Bit Test and Complement
<TR>
<TD>
<TD>MemWord,Imm8
<TD>0000111110111010oo111mmm
<TD>80386
<TD>Bit Test and Complement
<TR>
<TD>
<TD>RegWord,RegWord
<TD>0000111110111011oorrrmmm
<TD>80386
<TD>Bit Test and Complement
<TR>
<TD>
<TD>MemWord,RegWord
<TD>0000111110111011oorrrmmm
<TD>80386
<TD>Bit Test and Complement
<TR>
<TD>BTR
<TD>RegWord,Imm8
<TD>0000111110111010oo110mmm
<TD>80386
<TD>Bit Test and Reset
<TR>
<TD>
<TD>MemWord,Imm8
<TD>0000111110111010oo110mmm
<TD>80386
<TD>Bit Test and Reset
<TR>
<TD>
<TD>RegWord,RegWord
<TD>0000111110110011oorrrmmm
<TD>80386
<TD>Bit Test and Reset
<TR>
<TD>
<TD>MemWord,RegWord
<TD>0000111110110011oorrrmmm
<TD>80386
<TD>Bit Test and Reset
<TR>
<TD>BTS
<TD>RegWord,Imm8
<TD>0000111110111010oo101mmm
<TD>80386
<TD>Bit Test and Set
<TR>
<TD>
<TD>MemWord,Imm8
<TD>0000111110111010oo101mmm
<TD>80386
<TD>Bit Test and Set
<TR>
<TD>
<TD>RegWord,RegWord
<TD>0000111110101011oorrrmmm
<TD>80386
<TD>Bit Test and Set
<TR>
<TD>
<TD>MemWord,RegWord
<TD>0000111110101011oorrrmmm
<TD>80386
<TD>Bit Test and Set
<TR>
<TD><A NAME="HC">CBW</A>
<TD>
<TD>10011000
<TD>8086
<TD>Convert Byte to Word
<TR>
<TD>CDQ
<TD>
<TD>10011001
<TD>80386
<TD>Convert Doubleword to Quad-Word
<TR>
<TD>CLC
<TD>
<TD>11111000
<TD>8086
<TD>Clear Carry Flag (CF)
<TR>
<TD>CLD
<TD>
<TD>11111100
<TD>8086
<TD>Clear Direction Flag (DF)
<TR>
<TD>CLI
<TD>
<TD>11111010
<TD>8086
<TD>Clear Interrupt Flag (IF)
<TR>
<TD>CLTS
<TD>
<TD>0000111100000110
<TD>80286
<TD>Clear Task-Switched Flag in Control Register Zero
<TR>
<TD>CMC
<TD>
<TD>11110101
<TD>8086
<TD>Complementer Carry Flag (CF)
<TR>
<TD>CMOVcc
<TD>Reg,Reg
<TD>000011110100ccccoorrrmmm
<TD>PentiumPro
<TD>Conditional Move
<TR>
<TD>
<TD>Reg,Mem
<TD>000011110100ccccoorrrmmm
<TD>PentiumPro
<TD>Conditional Move
<TR>
<TD>CMP
<TD>Reg,Reg
<TD>0011101woorrrmmm
<TD>8086
<TD>Compare
<TR>
<TD>
<TD>Mem,Reg
<TD>0011100woorrrmmm
<TD>8086
<TD>Compare
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