📄 ether00.h
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#ifndef __ETHER00_H#define __ETHER00_H/* * Register definitions for the Ethernet MAC *//* * Copyright (c) Altera Corporation 2000. * All rights reserved. *//** Structures for the DMA controller*/typedef struct fda_desc { struct fda_desc * FDNext; long FDSystem; long FDStat; short FDLength; short FDCtl; }FDA_DESC;typedef struct buf_desc { char * BuffData; short BuffLength; char BDStat; char BDCtl; }BUF_DESC;/** Control masks for the DMA controller*/#define FDCTL_BDCOUNT_MSK (0x1F)#define FDCTL_BDCOUNT_OFST (0)#define FDCTL_FRMOPT_MSK (0x7C00)#define FDCTL_FRMOPT_OFST (10)#define FDCTL_COWNSFD_MSK (0x8000)#define FDCTL_COWNSFD_OFST (15)#define BDCTL_RXBDSEQN_MSK (0x7F)#define BDCTL_RXBDSEQN_OFST (0)#define BDCTL_COWNSBD_MSK (0x80)#define BDCTL_COWNSBD_OFST (7)#define FDNEXT_EOL_MSK (0x1)#define FDNEXT_EOL_OFST (0)#define FDNEXT_EOL_POINTER_MSK (0xFFFFFFF0)#define FDNEXT_EOL_POINTER_OFST (4)#define ETHER_ARC_SIZE (21)/** Regsiter definitions and masks*/#define ETHER_DMA_CTL(base) (ETHER00_TYPE (base + 0x100))#define ETHER_DMA_CTL_DMBURST_OFST (2)#define ETHER_DMA_CTL_DMBURST_MSK (0x1FC)#define ETHER_DMA_CTL_POWRMGMNT_OFST (11)#define ETHER_DMA_CTL_POWRMGMNT_MSK (0x1000)#define ETHER_DMA_CTL_TXBIGE_OFST (14)#define ETHER_DMA_CTL_TXBIGE_MSK (0x4000)#define ETHER_DMA_CTL_RXBIGE_OFST (15)#define ETHER_DMA_CTL_RXBIGE_MSK (0x8000)#define ETHER_DMA_CTL_TXWAKEUP_OFST (16)#define ETHER_DMA_CTL_TXWAKEUP_MSK (0x10000)#define ETHER_DMA_CTL_SWINTREQ_OFST (17)#define ETHER_DMA_CTL_SWINTREQ_MSK (0x20000)#define ETHER_DMA_CTL_INTMASK_OFST (18)#define ETHER_DMA_CTL_INTMASK_MSK (0x40000)#define ETHER_DMA_CTL_M66ENSTAT_OFST (19)#define ETHER_DMA_CTL_M66ENSTAT_MSK (0x80000)#define ETHER_DMA_CTL_RMTXINIT_OFST (20)#define ETHER_DMA_CTL_RMTXINIT_MSK (0x100000)#define ETHER_DMA_CTL_RMRXINIT_OFST (21)#define ETHER_DMA_CTL_RMRXINIT_MSK (0x200000)#define ETHER_DMA_CTL_RXALIGN_OFST (22)#define ETHER_DMA_CTL_RXALIGN_MSK (0xC00000)#define ETHER_DMA_CTL_RMSWRQ_OFST (24)#define ETHER_DMA_CTL_RMSWRQ_MSK (0x1000000)#define ETHER_DMA_CTL_RMEMBANK_OFST (25)#define ETHER_DMA_CTL_RMEMBANK_MSK (0x2000000)#define ETHER_TXFRMPTR(base) (ETHER00_TYPE (base + 0x104))#define ETHER_TXTHRSH(base) (ETHER00_TYPE (base + 0x308))#define ETHER_TXPOLLCTR(base) (ETHER00_TYPE (base + 0x30c))#define ETHER_BLFRMPTR(base) (ETHER00_TYPE (base + 0x110))#define ETHER_BLFFRMPTR_EOL_OFST (0)#define ETHER_BLFFRMPTR_EOL_MSK (0x1)#define ETHER_BLFFRMPTR_ADDRESS_OFST (4)#define ETHER_BLFFRMPTR_ADDRESS_MSK (0xFFFFFFF0)#define ETHER_RXFRAGSIZE(base) (ETHER00_TYPE (base + 0x114))#define ETHER_RXFRAGSIZE_MINFRAG_OFST (2)#define ETHER_RXFRAGSIZE_MINFRAG_MSK (0xFFC)#define ETHER_RXFRAGSIZE_ENPACK_OFST (15)#define ETHER_RXFRAGSIZE_ENPACK_MSK (0x8000)#define ETHER_INT_EN(base) (ETHER00_TYPE (base + 0x118))#define ETHER_INT_EN_FDAEXEN_OFST (0)#define ETHER_INT_EN_FDAEXEN_MSK (0x1)#define ETHER_INT_EN_BLEXEN_OFST (1)#define ETHER_INT_EN_BLEXN_MSK (0x2)#define ETHER_INT_EN_STARGABTEN_OFST (2)#define ETHER_INT_EN_STARGABTEN_MSK (0x4)#define ETHER_INT_EN_RTARGABTEN_OFST (3)#define ETHER_INT_EN_RTARGABTEN_MSK (0x8)#define ETHER_INT_EN_RMASABTEN_OFST (4)#define ETHER_INT_EN_RMASABTEN_MSK (0x10)#define ETHER_INT_EN_SSYSERREN_OFST (5)#define ETHER_INT_EN_SSYSERREN_MSK (0x20)#define ETHER_INT_EN_DPARERREN_OFST (6)#define ETHER_INT_EN_DPARERREN_MSK (0x40)#define ETHER_INT_EN_EARNOTEN_OFST (7)#define ETHER_INT_EN_EARNOTEN_MSK (0x80)#define ETHER_INT_EN_DPARDEN_OFST (8)#define ETHER_INT_EN_DPARDEN_MSK (0x100)#define ETHER_INT_EN_DMPARERREN_OFST (9)#define ETHER_INT_EN_DMPARERREN_MSK (0x200)#define ETHER_INT_EN_TXCTLCMPEN_OFST (10)#define ETHER_INT_EN_TXCTLCMPEN_MSK (0x400)#define ETHER_INT_EN_NRABTEN_OFST (11)#define ETHER_INT_EN_NRABTEN_MSK (0x800)#define ETHER_FDA_BAS(base) (ETHER00_TYPE (base + 0x11C))#define ETHER_FDA_BAS_ADDRESS_OFST (4)#define ETHER_FDA_BAS_ADDRESS_MSK (0xFFFFFFF0)#define ETHER_FDA_LIM(base) (ETHER00_TYPE (base + 0x120))#define ETHER_FDA_LIM_COUNT_OFST (4)#define ETHER_FDA_LIM_COUNT_MSK (0xFFF0)#define ETHER_INT_SRC(base) (ETHER00_TYPE (base + 0x124))#define ETHER_INT_SRC_INTMACTX_OFST (0)#define ETHER_INT_SRC_INTMACTX_MSK (0x1)#define ETHER_INT_SRC_INTMACRX_OFST (1)#define ETHER_INT_SRC_INTMACRX_MSK (0x2)#define ETHER_INT_SRC_INTSBUS_OFST (2)#define ETHER_INT_SRC_INTSBUS_MSK (0x4)#define ETHER_INT_SRC_INTFDAEX_OFST (3)#define ETHER_INT_SRC_INTFDAEX_MSK (0x8)#define ETHER_INT_SRC_INTBLEX_OFST (4)#define ETHER_INT_SRC_INTBLEX_MSK (0x10)#define ETHER_INT_SRC_SWINT_OFST (5)#define ETHER_INT_SRC_SWINT_MSK (0x20)#define ETHER_INT_SRC_INTEARNOT_OFST (6)#define ETHER_INT_SRC_INTEARNOT_MSK (0x40)#define ETHER_INT_SRC_DMPARERR_OFST (7)#define ETHER_INT_SRC_DMPARERR_MSK (0x80)#define ETHER_INT_SRC_INTEXBD_OFST (8)#define ETHER_INT_SRC_INTEXBD_MSK (0x100)#define ETHER_INT_SRC_INTTXCTLCMP_OFST (9)#define ETHER_INT_SRC_INTTXCTLCMP_MSK (0x200)#define ETHER_INT_SRC_INTNRABT_OFST (10)#define ETHER_INT_SRC_INTNRABT_MSK (0x400)#define ETHER_INT_SRC_FDAEX_OFST (11)#define ETHER_INT_SRC_FDAEX_MSK (0x800)#define ETHER_INT_SRC_BLEX_OFST (12)#define ETHER_INT_SRC_BLEX_MSK (0x1000)#define ETHER_INT_SRC_DMPARERRSTAT_OFST (13)#define ETHER_INT_SRC_DMPARERRSTAT_MSK (0x2000)#define ETHER_INT_SRC_NRABT_OFST (14)#define ETHER_INT_SRC_NRABT_MSK (0x4000)#define ETHER_INT_SRC_INTLINK_OFST (15)#define ETHER_INT_SRC_INTLINK_MSK (0x8000)#define ETHER_INT_SRC_INTEXDEFER_OFST (16)#define ETHER_INT_SRC_INTEXDEFER_MSK (0x10000)#define ETHER_INT_SRC_INTRMON_OFST (17)#define ETHER_INT_SRC_INTRMON_MSK (0x20000)#define ETHER_INT_SRC_IRQ_MSK (0x83FF)#define ETHER_PAUSECNT(base) (ETHER00_TYPE (base + 0x40))#define ETHER_PAUSECNT_COUNT_OFST (0)#define ETHER_PAUSECNT_COUNT_MSK (0xFFFF)#define ETHER_REMPAUCNT(base) (ETHER00_TYPE (base + 0x44))#define ETHER_REMPAUCNT_COUNT_OFST (0)#define ETHER_REMPAUCNT_COUNT_MSK (0xFFFF)#define ETHER_TXCONFRMSTAT(base) (ETHER00_TYPE (base + 0x348))#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST (0)#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK (0x3FFFFF)#define ETHER_MAC_CTL(base) (ETHER00_TYPE (base + 0))#define ETHER_MAC_CTL_HALTREQ_OFST (0)#define ETHER_MAC_CTL_HALTREQ_MSK (0x1)#define ETHER_MAC_CTL_HALTIMM_OFST (1)#define ETHER_MAC_CTL_HALTIMM_MSK (0x2)#define ETHER_MAC_CTL_RESET_OFST (2)#define ETHER_MAC_CTL_RESET_MSK (0x4)#define ETHER_MAC_CTL_FULLDUP_OFST (3)#define ETHER_MAC_CTL_FULLDUP_MSK (0x8)#define ETHER_MAC_CTL_MACLOOP_OFST (4)#define ETHER_MAC_CTL_MACLOOP_MSK (0x10)#define ETHER_MAC_CTL_CONN_OFST (5)#define ETHER_MAC_CTL_CONN_MSK (0x60)#define ETHER_MAC_CTL_LOOP10_OFST (7)#define ETHER_MAC_CTL_LOOP10_MSK (0x80)#define ETHER_MAC_CTL_LNKCHG_OFST (8)#define ETHER_MAC_CTL_LNKCHG_MSK (0x100)#define ETHER_MAC_CTL_MISSROLL_OFST (10)#define ETHER_MAC_CTL_MISSROLL_MSK (0x400)#define ETHER_MAC_CTL_ENMISSROLL_OFST (13)#define ETHER_MAC_CTL_ENMISSROLL_MSK (0x2000)#define ETHER_MAC_CTL_LINK10_OFST (15)#define ETHER_MAC_CTL_LINK10_MSK (0x8000)#define ETHER_ARC_CTL(base) (ETHER00_TYPE (base + 0x4))#define ETHER_ARC_CTL_STATIONACC_OFST (0)#define ETHER_ARC_CTL_STATIONACC_MSK (0x1)#define ETHER_ARC_CTL_GROUPACC_OFST (1)#define ETHER_ARC_CTL_GROUPACC_MSK (0x2)#define ETHER_ARC_CTL_BROADACC_OFST (2)#define ETHER_ARC_CTL_BROADACC_MSK (0x4)#define ETHER_ARC_CTL_NEGARC_OFST (3)#define ETHER_ARC_CTL_NEGARC_MSK (0x8)#define ETHER_ARC_CTL_COMPEN_OFST (4)#define ETHER_ARC_CTL_COMPEN_MSK (0x10)#define ETHER_TX_CTL(base) (ETHER00_TYPE (base + 0x8))#define ETHER_TX_CTL_TXEN_OFST (0)#define ETHER_TX_CTL_TXEN_MSK (0x1)#define ETHER_TX_CTL_TXHALT_OFST (1)#define ETHER_TX_CTL_TXHALT_MSK (0x2)#define ETHER_TX_CTL_NOPAD_OFST (2)#define ETHER_TX_CTL_NOPAD_MSK (0x4)#define ETHER_TX_CTL_NOCRC_OFST (3)#define ETHER_TX_CTL_NOCRC_MSK (0x8)#define ETHER_TX_CTL_FBACK_OFST (4)#define ETHER_TX_CTL_FBACK_MSK (0x10)#define ETHER_TX_CTL_NOEXDEF_OFST (5)#define ETHER_TX_CTL_NOEXDEF_MSK (0x20)#define ETHER_TX_CTL_SDPAUSE_OFST (6)#define ETHER_TX_CTL_SDPAUSE_MSK (0x40)#define ETHER_TX_CTL_MII10_OFST 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