proc-sa110.s

广州斯道2410普及版II的源代码

	mov	r1, #PAGESIZE
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #DCACHELINESIZE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #DCACHELINESIZE
	subs	r1, r1, #2 * DCACHELINESIZE
	bne	1b
	mov	pc, lr

/*
 * cpu_sa110_dcache_clean_entry(addr)
 *
 * Clean the specified entry of any caches such that the MMU
 * translation fetches will obtain correct data.
 *
 * addr: cache-unaligned virtual address
 */
	.align	5
ENTRY(cpu_sa110_dcache_clean_entry)
ENTRY(cpu_sa1100_dcache_clean_entry)
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/* ================================ I-CACHE =============================== */

/*
 * cpu_sa110_icache_invalidate_range(start, end)
 *
 * invalidate a range of virtual addresses from the Icache
 *
 * start: virtual start address
 * end:   virtual end address
 */
	.align	5
ENTRY(cpu_sa110_icache_invalidate_range)
ENTRY(cpu_sa1100_icache_invalidate_range)
	bic	r0, r0, #DCACHELINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ Clean D entry
	add	r0, r0, #DCACHELINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
ENTRY(cpu_sa110_icache_invalidate_page)
ENTRY(cpu_sa1100_icache_invalidate_page)
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mov	pc, lr

/* ================================== TLB ================================= */

/*
 * cpu_sa110_tlb_invalidate_all()
 *
 * Invalidate all TLB entries
 */
	.align	5
ENTRY(cpu_sa110_tlb_invalidate_all)
ENTRY(cpu_sa1100_tlb_invalidate_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I & D TLBs
	mov	pc, lr

/*
 * cpu_sa110_tlb_invalidate_range(start, end)
 *
 * invalidate TLB entries covering the specified range
 *
 * start: range start address
 * end:   range end address
 */
	.align	5
ENTRY(cpu_sa110_tlb_invalidate_range)
ENTRY(cpu_sa1100_tlb_invalidate_range)
	bic	r0, r0, #0x0ff
	bic	r0, r0, #0xf00
	sub	r3, r1, r0
	cmp	r3, #256 * PAGESIZE		@ arbitary, should be tuned
	bhi	cpu_sa110_tlb_invalidate_all
	mov	r3, #0
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
1:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
	add	r0, r0, #PAGESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r3, c8, c5, 0		@ invalidate I TLB
	mov	pc, lr

/*
 * cpu_sa110_tlb_invalidate_page(page, flags)
 *
 * invalidate the TLB entries for the specified page.
 *
 * page:  page to invalidate
 * flags: non-zero if we include the I TLB
 */
	.align	5
ENTRY(cpu_sa110_tlb_invalidate_page)
ENTRY(cpu_sa1100_tlb_invalidate_page)
	mov	r3, #0
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
	teq	r1, #0
	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
	mcrne	p15, 0, r3, c8, c5, 0		@ invalidate I TLB
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_sa110_set_pgd(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_sa110_set_pgd)
	ldr	r3, =Lclean_switch
	ldr	ip, =FLUSH_BASE
	ldr	r2, [r3]
	ands	r2, r2, #1
	eor	r2, r2, #1
	str	r2, [r3]
	addne	ip, ip, #FLUSH_OFFSET
	flush_110_dcache	r3, ip, r1
	mov	r1, #0
	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs
	mov	pc, lr

/*
 * cpu_sa1100_set_pgd(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_sa1100_set_pgd)
	ldr	r3, =Lclean_switch
	ldr	ip, =FLUSH_BASE
	ldr	r2, [r3]
	ands	r2, r2, #1
	eor	r2, r2, #1
	str	r2, [r3]
	addne	ip, ip, #FLUSH_OFFSET
	flush_1100_dcache	r3, ip, r1
	mov	ip, #0
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
	mov	pc, lr

/*
 * cpu_sa110_set_pmd(pmdp, pmd)
 *
 * Set a level 1 translation table entry, and clean it out of
 * any caches such that the MMUs can load it correctly.
 *
 * pmdp: pointer to PMD entry
 * pmd:  PMD value to store
 */
	.align	5
ENTRY(cpu_sa110_set_pmd)
ENTRY(cpu_sa1100_set_pmd)
	str	r1, [r0]
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 * cpu_sa110_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_sa110_set_pte)
ENTRY(cpu_sa1100_set_pte)
	str	r1, [r0], #-1024		@ linux version

	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY

	bic	r2, r1, #0xff0
	bic	r2, r2, #3
	orr	r2, r2, #HPTE_TYPE_SMALL

	tst	r1, #LPTE_USER | LPTE_EXEC	@ User or Exec?
	orrne	r2, r2, #HPTE_AP_READ

	tst	r1, #LPTE_WRITE | LPTE_DIRTY	@ Write and Dirty?
	orreq	r2, r2, #HPTE_AP_WRITE

	tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young?
	movne	r2, #0

	str	r2, [r0]			@ hardware version
	mov	r0, r0
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr


cpu_manu_name:
	.asciz	"Intel"
cpu_sa110_name:
	.asciz	"StrongARM-110"
cpu_sa1100_name:
	.asciz	"StrongARM-1100"
cpu_sa1110_name:
	.asciz	"StrongARM-1110"
	.align

	.section ".text.init", #alloc, #execinstr

__sa1100_setup:	@ Allow read-buffer operations from userland
	mcr	p15, 0, r0, c9, c0, 5
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, #0x0e00			@ ..VI ZFRS BLDP WCAM
	bic	r0, r0, #0x0002			@ .... 000. .... ..0.
	orr	r0, r0, #0x003d
	orr	r0, r0, #0x3100			@ ..11 ...1 ..11 11.1
	b	__setup_common

__sa110_setup:
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, #0x2e00			@ ..VI ZFRS BLDP WCAM
	bic	r0, r0, #0x0002			@ ..0. 000. .... ..0.
	orr	r0, r0, #0x003d
	orr	r0, r0, #0x1100			@ ...1 ...1 ..11 11.1
__setup_common:
	mov	r10, #0
	mcr	p15, 0, r10, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r10, c7, c10, 4		@ drain write buffer on v4
	mcr	p15, 0, r10, c8, c7		@ invalidate I,D TLBs on v4
	mcr	p15, 0, r4, c2, c0		@ load page table pointer
	mov	r10, #0x1f			@ Domains 0, 1 = client
	mcr	p15, 0, r10, c3, c0		@ load domain access register
	mov	pc, lr

	.text

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */

	.type	sa110_processor_functions, #object
ENTRY(sa110_processor_functions)
	.word	cpu_sa110_data_abort
	.word	cpu_sa110_check_bugs
	.word	cpu_sa110_proc_init
	.word	cpu_sa110_proc_fin
	.word	cpu_sa110_reset
	.word	cpu_sa110_do_idle

	/* cache */
	.word	cpu_sa110_cache_clean_invalidate_all
	.word	cpu_sa110_cache_clean_invalidate_range
	.word	cpu_sa110_flush_ram_page

	/* dcache */
	.word	cpu_sa110_dcache_invalidate_range
	.word	cpu_sa110_dcache_clean_range
	.word	cpu_sa110_dcache_clean_page
	.word	cpu_sa110_dcache_clean_entry

	/* icache */
	.word	cpu_sa110_icache_invalidate_range
	.word	cpu_sa110_icache_invalidate_page

	/* tlb */
	.word	cpu_sa110_tlb_invalidate_all
	.word	cpu_sa110_tlb_invalidate_range
	.word	cpu_sa110_tlb_invalidate_page

	/* pgtable */
	.word	cpu_sa110_set_pgd
	.word	cpu_sa110_set_pmd
	.word	cpu_sa110_set_pte
	.size	sa110_processor_functions, . - sa110_processor_functions

	.type	cpu_sa110_info, #object
cpu_sa110_info:
	.long	cpu_manu_name
	.long	cpu_sa110_name
	.size	cpu_sa110_info, . - cpu_sa110_info


/*
 * SA1100 and SA1110 share the same function calls
 */
	.type	sa1100_processor_functions, #object
ENTRY(sa1100_processor_functions)
	.word	cpu_sa1100_data_abort
	.word	cpu_sa1100_check_bugs
	.word	cpu_sa1100_proc_init
	.word	cpu_sa1100_proc_fin
	.word	cpu_sa1100_reset
	.word	cpu_sa1100_do_idle

	/* cache */
	.word	cpu_sa1100_cache_clean_invalidate_all
	.word	cpu_sa1100_cache_clean_invalidate_range
	.word	cpu_sa1100_flush_ram_page

	/* dcache */
	.word	cpu_sa1100_dcache_invalidate_range
	.word	cpu_sa1100_dcache_clean_range
	.word	cpu_sa1100_dcache_clean_page
	.word	cpu_sa1100_dcache_clean_entry

	/* icache */
	.word	cpu_sa1100_icache_invalidate_range
	.word	cpu_sa1100_icache_invalidate_page

	/* tlb */
	.word	cpu_sa1100_tlb_invalidate_all
	.word	cpu_sa1100_tlb_invalidate_range
	.word	cpu_sa1100_tlb_invalidate_page

	/* pgtable */
	.word	cpu_sa1100_set_pgd
	.word	cpu_sa1100_set_pmd
	.word	cpu_sa1100_set_pte
	.size	sa1100_processor_functions, . - sa1100_processor_functions

cpu_sa1100_info:
	.long	cpu_manu_name
	.long	cpu_sa1100_name
	.size	cpu_sa1100_info, . - cpu_sa1100_info

cpu_sa1110_info:
	.long	cpu_manu_name
	.long	cpu_sa1110_name
	.size	cpu_sa1110_info, . - cpu_sa1110_info

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv4"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v4"
	.size	cpu_elf_name, . - cpu_elf_name
	.align

	.section ".proc.info", #alloc, #execinstr

	.type	__sa110_proc_info,#object
__sa110_proc_info:
	.long	0x4401a100
	.long	0xfffffff0
	.long	0x00000c0e
	b	__sa110_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
	.long	cpu_sa110_info
	.long	sa110_processor_functions
	.size	__sa110_proc_info, . - __sa110_proc_info

	.type	__sa1100_proc_info,#object
__sa1100_proc_info:
	.long	0x4401a110
	.long	0xfffffff0
	.long	0x00000c0e
	b	__sa1100_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
	.long	cpu_sa1100_info
	.long	sa1100_processor_functions
	.size	__sa1100_proc_info, . - __sa1100_proc_info

	.type	__sa1110_proc_info,#object
__sa1110_proc_info:
	.long	0x6901b110
	.long	0xfffffff0
	.long	0x00000c0e
	b	__sa1100_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
	.long	cpu_sa1110_info
	.long	sa1100_processor_functions
	.size	__sa1110_proc_info, . - __sa1110_proc_info