proc-arm1020.s

广州斯道2410普及版II的源代码

/*
 *  linux/arch/arm/mm/arm1020.S: MMU functions for ARM1020
 *
 *  Copyright (C) 2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm1020.
 */
#include <linux/linkage.h>
#include <linux/config.h>
#include <asm/assembler.h>
#include <asm/constants.h>
#include <asm/procinfo.h>
#include <asm/hardware.h>

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define MAX_AREA_SIZE	32768

/*
 * the cache line size of the I and D cache
 */
#define DCACHELINESIZE	32
#define ICACHELINESIZE	32

/*
 * and the page size
 */
#define PAGESIZE	4096

	.text

/*
 * cpu_arm1020_data_abort()
 *
 * obtain information about current aborted instruction
 * Note: we read user space.  This means we might cause a data
 * abort here if the I-TLB and D-TLB aren't seeing the same
 * picture.  Unfortunately, this does happen.  We live with it.
 *
 *  r2 = address of aborted instruction
 *  r3 = cpsr
 *
 * Returns:
 *  r0 = address of abort
 *  r1 != 0 if writing
 *  r3 = FSR
 *  r4 = corrupted
 */
	.align	5
ENTRY(cpu_arm1020_data_abort)
	mrc	p15, 0, r3, c5, c0, 0		@ get FSR
	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
	ldr	r1, [r2]			@ read aborted instruction
	and	r3, r3, #255
	tst	r1, r1, lsr #21 		@ C = bit 20
	sbc	r1, r1, r1			@ r1 = C - 1
	mov	pc, lr

/*
 * cpu_arm1020_check_bugs()
 */
ENTRY(cpu_arm1020_check_bugs)
	mrs	ip, cpsr
	bic	ip, ip, #F_BIT
	msr	cpsr, ip
	mov	pc, lr

/*
 * cpu_arm1020_proc_init()
 */
ENTRY(cpu_arm1020_proc_init)
	mov	pc, lr

/*
 * cpu_arm1020_proc_fin()
 */
ENTRY(cpu_arm1020_proc_fin)
	stmfd	sp!, {lr}
	mov	ip, #F_BIT | I_BIT | SVC_MODE
	msr	cpsr_c, ip
	bl	cpu_arm1020_cache_clean_invalidate_all
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000 		@ ...i............
	bic	r0, r0, #0x000e 		@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ldmfd	sp!, {pc}

/*
 * cpu_arm1020_reset(loc)
 *
 * Perform a soft reset of the system.	Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm1020_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f 		@ ............wcam
	bic	ip, ip, #0x1100 		@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm1020_do_idle()
 */
	.align	5
ENTRY(cpu_arm1020_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
	mov	r0, r0
#endif
	mov	pc, lr

/* ================================= CACHE ================================ */


/*
 * cpu_arm1020_cache_clean_invalidate_all()
 *
 * clean and invalidate all cache lines
 *
 * Note:
 *  1. we should preserve r0 at all times
 */
	.align	5
ENTRY(cpu_arm1020_cache_clean_invalidate_all)
	mov	r2, #1
cpu_arm1020_cache_clean_invalidate_all_r2:
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
	mcr	p15, 0, ip, c7, c10, 4

	mov	r1, #0xf			@ 16 segments
1:	mov	r3, #0x3F			@ 64 entries
2:	mov	ip, r3, LSL #26 		@ shift up entry
	orr	ip, ip, r1, LSL #5		@ shift in/up index
	mcr	p15, 0, ip, c7, c14, 2		@ Clean & Inval DCache entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB 
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	ip, ip
#endif
	subs	r3, r3, #1
	cmp	r3, #0
	bge	2b				@ entries 3F to 0
	subs	r1, r1, #1
	cmp	r1, #0
	bge	1b				@ segments 7 to 0
#endif
        
#ifdef CONFIG_CPU_ARM1020_I_CACHE_ON
	teq	r2, #0
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	ip, ip
	mov	ip, ip
#endif
	mov	pc, lr

/*
 * cpu_arm1020_cache_clean_invalidate_range(start, end, flags)
 *
 * clean and invalidate all cache lines associated with this area of memory
 *
 * start: Area start address
 * end:   Area end address
 * flags: nonzero for I cache as well
 */
	.align	5
ENTRY(cpu_arm1020_cache_clean_invalidate_range)
	bic	r0, r0, #DCACHELINESIZE - 1
	sub	r3, r1, r0
	cmp	r3, #MAX_AREA_SIZE
	bgt	cpu_arm1020_cache_clean_invalidate_all_r2
	mcr	p15, 0, r3, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
	add	r0, r0, #DCACHELINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
#endif
	add	r0, r0, #DCACHELINESIZE
	cmp	r0, r1
	blt	1b
#endif

#ifdef CONFIG_CPU_ARM1020_I_CACHE_ON
	teq	r2, #0
	movne	r0, #0
	mcrne	p15, 0, r0, c7, c5, 0		@ invalidate I cache
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
	mov	r0, r0
#endif
#endif
	mov	pc, lr

/*
 * cpu_arm1020_flush_ram_page(page)
 *
 * clean and invalidate all cache lines associated with this area of memory
 *
 * page: page to clean and invalidate
 */
	.align	5
ENTRY(cpu_arm1020_flush_ram_page)
	mcr	p15, 0, r1, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
	mov	r1, #PAGESIZE
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	add	r0, r0, #DCACHELINESIZE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
	mov	r0, r0
#endif
	subs	r1, r1, #2 * DCACHELINESIZE
	bne	1b
	mov	r0, #0

#endif
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
	mov	r0, r0
#endif
	mov	pc, lr

/* ================================ D-CACHE =============================== */

/*
 * cpu_arm1020_dcache_invalidate_range(start, end)
 *
 * throw away all D-cached data in specified region without an obligation
 * to write them back.	Note however that we must clean the D-cached entries
 * around the boundaries if the start and/or end address are not cache
 * aligned.
 *
 * start: virtual start address
 * end:   virtual end address
 */
	.align	5
ENTRY(cpu_arm1020_dcache_invalidate_range)
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
	/* D cache are on */
	tst	r0, #DCACHELINESIZE - 1
	bic	r0, r0, #DCACHELINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 4
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry at start
	mcrne	p15, 0, r0, c7, c10, 4		@ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
	mov	r0, r0
#endif
	tst	r1, #DCACHELINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 4
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry at end
	mcrne	p15, 0, r1, c7, c10, 4		@ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r1, r1
	mov	r1, r1
	mov	r1, r1
#endif
        
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
#endif
	add	r0, r0, #DCACHELINESIZE
	cmp	r0, r1
	blt	1b
#else
	/* D cache off, but still drain the write buffer */
	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
	mov	r0, r0
#endif
#endif
	mov	pc, lr

/*
 * cpu_arm1020_dcache_clean_range(start, end)
 *
 * For the specified virtual address range, ensure that all caches contain
 * clean data, such that peripheral accesses to the physical RAM fetch
 * correct data.
 *
 * start: virtual start address
 * end:   virtual end address
 */
	.align	5
ENTRY(cpu_arm1020_dcache_clean_range)
	bic	r0, r0, #DCACHELINESIZE - 1
	sub	r3, r1, r0
	cmp	r3, #MAX_AREA_SIZE
	bgt	cpu_arm1020_cache_clean_invalidate_all_r2
	mcr	p15, 0, r3, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
	add	r0, r0, #DCACHELINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
#endif
	add	r0, r0, #DCACHELINESIZE
	cmp	r0, r1
	blt	1b
#endif

#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
	mov	r0, r0
#endif
	mov	pc, lr

/*
 * cpu_arm1020_dcache_clean_page(page)
 *
 * Cleans a single page of dcache so that if we have any future aliased
 * mappings, they will be consistent at the time that they are created.
 *
 * page: virtual address of page to clean from dcache
 *
 * Note:
 *  1. we don't need to flush the write buffer in this case.
 *  2. we don't invalidate the entries since when we write the page
 *     out to disk, the entries may get reloaded into the cache.
 */
	.align	5
ENTRY(cpu_arm1020_dcache_clean_page)
	mov	r1, #PAGESIZE
	mcr	p15, 0, r0, c7, c10, 4
#ifdef CONFIG_CPU_ARM1020_D_CACHE_ON
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry  (drain is done by TLB fns)
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
#endif
	add	r0, r0, #DCACHELINESIZE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION
	mov	r0, r0
#endif
	add	r0, r0, #DCACHELINESIZE
	subs	r1, r1, #2 * DCACHELINESIZE
	bhi	1b
#endif
#ifdef CONFIG_CPU_ARM1020_BRANCH_PREDICTION