xdma_channel.h

来自「linux嵌入式系统的dma方式的实现代码」· C头文件 代码 · 共 349 行 · 第 1/2 页

#include "xstatus.h"
#include "xversion.h"
#include "xbuf_descriptor.h"
#include "xdma_channel_i.h"     /* constants shared with buffer descriptor */

/************************** Constant Definitions *****************************/

/** @name DMA control register bit fields
 *
 * the following constants provide access to the bit fields of the DMA control
 * register (DMACR)
 * @{
 */
#define XDC_DMACR_SOURCE_INCR_MASK   0x80000000UL /**< increment source address */
#define XDC_DMACR_DEST_INCR_MASK     0x40000000UL /**< increment dest address */
#define XDC_DMACR_SOURCE_LOCAL_MASK  0x20000000UL /**< local source address */
#define XDC_DMACR_DEST_LOCAL_MASK    0x10000000UL /**< local dest address */
#define XDC_DMACR_SG_DISABLE_MASK    0x08000000UL /**< scatter gather disable */
#define XDC_DMACR_GEN_BD_INTR_MASK   0x04000000UL /**< descriptor interrupt */
#define XDC_DMACR_LAST_BD_MASK       XDC_CONTROL_LAST_BD_MASK /**< last buffer
                                                                   descriptor */
#define XDC_DMACR_DRE_MODE_MASK      0x01000000UL /**< DRE/normal mode */

#define XDC_DMACR_TX_CS_INIT_MASK    0x0000FFFFUL /**< Initial value for TX
                                                       CS offload */
#define XDC_DMACR_CS_OFFLOAD_MASK    0x00800000UL /**< Enable CS offload */
/* @} */

/** @name DMA status register bit fields
 *
 * the following constants provide access to the bit fields of the DMA status
 * register (DMASR)
 * @{
 */
#define XDC_DMASR_BUSY_MASK          0x80000000UL /**< channel is busy */
#define XDC_DMASR_BUS_ERROR_MASK     0x40000000UL /**< bus error occurred */
#define XDC_DMASR_BUS_TIMEOUT_MASK   0x20000000UL /**< bus timeout occurred */
#define XDC_DMASR_LAST_BD_MASK       XDC_STATUS_LAST_BD_MASK /**< last buffer
                                                                  descriptor */
#define XDC_DMASR_SG_BUSY_MASK       0x08000000UL /**< scatter gather is busy */

#define XDC_DMACR_RX_CS_RAW_MASK     0xFFFF0000UL /**< RAW CS value for RX data */
/* @} */

/** @name DMA destination address register bit fields when checksum offload is
 * used
 *
 * the following constants provide access to the bit fields of the
 * Destination Address Register (DAREG)
 * @{
 */
#define XDC_DAREG_CS_BEGIN_MASK      0xFFFF0000UL /**< byte position to begin
                                                       checksum calculation*/
#define XDC_DAREG_CS_INSERT_MASK     0x0000FFFFUL /**< byte position to place
                                                       calculated checksum */
/** @name Interrupt Status/Enable Register bit fields
 *
 * the following constants provide access to the bit fields of the interrupt
 * status register (ISR) and the interrupt enable register (IER), bit masks
 * match for both registers such that they are named IXR
 * @{
 */
#define XDC_IXR_DMA_DONE_MASK       0x1UL  /**< dma operation done */
#define XDC_IXR_DMA_ERROR_MASK      0x2UL  /**< dma operation error */
#define XDC_IXR_PKT_DONE_MASK       0x4UL  /**< packet done */
#define XDC_IXR_PKT_THRESHOLD_MASK  0x8UL  /**< packet count threshold */
#define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL /**< packet wait bound reached */
#define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL /**< scatter gather disable
                                                acknowledge occurred */
#define XDC_IXR_SG_END_MASK         0x40UL /**< last buffer descriptor
                                                disabled scatter gather */
#define XDC_IXR_BD_MASK             0x80UL /**< buffer descriptor done */
/* @} */

/**************************** Type Definitions *******************************/

/**
 * the following structure contains data which is on a per instance basis
 * for the XDmaChannel component
 */
typedef struct XDmaChannelTag
{
    XVersion Version;               /**< version of the driver */
    Xuint32 RegBaseAddress;         /**< base address of registers */
    Xuint32 IsReady;                /**< device is initialized and ready */

    XBufDescriptor *PutPtr;         /**< keep track of where to put into list */
    XBufDescriptor *GetPtr;         /**< keep track of where to get from list */
    XBufDescriptor *CommitPtr;      /**< keep track of where to commit in list */
    XBufDescriptor *LastPtr;        /**< keep track of the last put in the list */
    Xuint32 TotalDescriptorCount;   /**< total # of descriptors in the list */
    Xuint32 ActiveDescriptorCount;  /**< # of descriptors pointing to buffers
                                         in the buffer descriptor list */
    Xuint32 ActivePacketCount;      /**< # of packets that have been put into
                                         the list and transmission confirmation
                                         have not been received by the driver */
    Xboolean Committed;             /**< CommitPuts is called? */

} XDmaChannel;

/***************** Macros (Inline Functions) Definitions *********************/


/************************** Function Prototypes ******************************/

/**
 * Standard functions
 */
XStatus XDmaChannel_Initialize(XDmaChannel *InstancePtr,
                               Xuint32 BaseAddress);
Xboolean XDmaChannel_IsReady(XDmaChannel *InstancePtr);
XVersion *XDmaChannel_GetVersion(XDmaChannel *InstancePtr);
XStatus XDmaChannel_SelfTest(XDmaChannel *InstancePtr);
void XDmaChannel_Reset(XDmaChannel *InstancePtr);

/**
 * Control functions
 */
Xuint32 XDmaChannel_GetControl(XDmaChannel *InstancePtr);
void XDmaChannel_SetControl(XDmaChannel *InstancePtr, Xuint32 Control);

/**
 * Status functions
 */
Xuint32 XDmaChannel_GetStatus(XDmaChannel *InstancePtr);
void XDmaChannel_SetIntrStatus(XDmaChannel *InstancePtr, Xuint32 Status);
Xuint32 XDmaChannel_GetIntrStatus(XDmaChannel *InstancePtr);
void XDmaChannel_SetIntrEnable(XDmaChannel *InstancePtr, Xuint32 Enable);
Xuint32 XDmaChannel_GetIntrEnable(XDmaChannel *InstancePtr);

/**
 * DMA without scatter gather functions
 */
void XDmaChannel_Transfer(XDmaChannel *InstancePtr,
                          Xuint32 *SourcePtr,
                          Xuint32 *DestinationPtr,
                          Xuint32 ByteCount);

/**
 * Scatter gather functions
 */
XStatus XDmaChannel_SgStart(XDmaChannel *InstancePtr);
XStatus XDmaChannel_SgStop(XDmaChannel *InstancePtr,
                           XBufDescriptor **BufDescriptorPtr);
XStatus XDmaChannel_CreateSgList(XDmaChannel *InstancePtr,
                                 Xuint32 *MemoryPtr,
                                 Xuint32 ByteCount);
Xboolean XDmaChannel_IsSgListEmpty(XDmaChannel *InstancePtr);

XStatus XDmaChannel_PutDescriptor(XDmaChannel *InstancePtr,
                                  XBufDescriptor *BufDescriptorPtr);
XStatus XDmaChannel_CommitPuts(XDmaChannel *InstancePtr);
XStatus XDmaChannel_GetDescriptor(XDmaChannel *InstancePtr,
                                  XBufDescriptor** BufDescriptorPtr);

/**
 * Packet functions for interrupt coalescing
 */
Xuint32 XDmaChannel_GetPktCount(XDmaChannel *InstancePtr);
void XDmaChannel_DecrementPktCount(XDmaChannel *InstancePtr);
XStatus XDmaChannel_SetPktThreshold(XDmaChannel *InstancePtr,
                                    Xuint8 Threshold);
Xuint8 XDmaChannel_GetPktThreshold(XDmaChannel *InstancePtr);
void XDmaChannel_SetPktWaitBound(XDmaChannel *InstancePtr,
                                 Xuint32 WaitBound);
Xuint32 XDmaChannel_GetPktWaitBound(XDmaChannel *InstancePtr);


#ifdef __cplusplus
}
#endif

#endif              /* end of protection macro */