l2_cpu.c

凌阳MP3 spSPCA755yuanma

/*++

Copyright (c) 2001 Sunplus Technology Co., Ltd.

Module Name:

        L2_cpu.c

Abstract:

        Module related to L2 CPU functions

Environment:

        Keil C51 Compiler

Revision History:

        11/12/2001      WZH    created                 

--*/
//=============================================================================
//Header file
//=============================================================================
#include "general.h"
#include "main.h"

//=============================================================================
//Symbol
//=============================================================================
//-----------------------------------------------------------------------------
//Constant
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
//Variable
//-----------------------------------------------------------------------------
sfr RamPage = 0x9B;
sfr MemStretch = 0x8E;
xdata  UCHAR CPUIO_STATUS[17];
//=============================================================================
//Program       
//=============================================================================

//-----------------------------------------------------------------------------
//L2_InitCPU
//-----------------------------------------------------------------------------
/* 
routine description:
        cpu interface hardware initialization
arguments:
        CamMode: camera operation mode
return value:
        0x00   - success
        others - error
*/
// SGJM UCHAR L2_InitCPU(UCHAR CamMode) USING_0
void L2_InitCPU(void)
{
        //PRINT_L2("        L2_InitCPU: Enter L2_InitCPU\n");

        // SGJM DEL if(CamMode > 6) return 0x01;

       //SGJM DEL  if(CamMode == 0)
        {
                MemStretch = 0x00;                        // memory stretch = 0
       	        XBYTE[0x2100] = 0x0F;                     // rampageen, rompageen, SRAM page disable for Maskcode
//     	        XBYTE[0x2006] = 0x55;                     // PLL Select
           	    XBYTE[0x2024] = 0x02;                     // CPU clock
                if(L2K_CPUInternal == 1)
                {
							P1 &= 0xFB;
                     XBYTE[0x2102] = 0xfd;               // P1 & P3 are always drive
						//P10 input------used for battery option
						//P11 output-----used for TI1770 MD
						//-----
						//P12 output-----used for TI1770 MC
						//P13 output-----used for TI1770 MS
						//P14 output-----used for TI1770 PD
						//P15 output-----used for DAC power control
						//P16 output-----used for A LED
						//P17 output-----used for B LED
						// SGJM DEL G_Battery_GroupNum = P1 & 0x01;//select battery group

                        XBYTE[0x2103] = 0x0f;         //P3.0 is charge pin-----output enable
                        //P1 = 0xff;
                        //P3 = 0xff;
                }
                else
                {
                        XBYTE[0x2102] = 0x00;
                        XBYTE[0x2103] = 0x00;
                }
                if(L2K_CPUP1 == 1)
					{
                        XBYTE[0x201B] = (XBYTE[0X201B] | 0x02); // P1 is used for GPIO
                        XBYTE[0x201A] = (XBYTE[0X201A] & 0x62); // P3.6/P3.7 is used for GPIO
					}
                else
                     XBYTE[0x201B] = (XBYTE[0X201B] | 0x02);

                RamPage = 0x00;
        }

        //PRINT_L2("        L2_InitCPU: Exit L2_InitCPU\n");

      //SGJM DEL   return L2K_SUCCESS;
}

//-----------------------------------------------------------------------------
//L2_Set4KSRAMMode
//-----------------------------------------------------------------------------
/*
routine description:
        high bank 4k sram mode selection
arguments:
        Mode: 0: addressible SRAM (0x1000 - 0x1FFF)
              1: access data port (0x2C10) (0x0000 - 0x0FFF)
              2: used for DMA buffer (0x0000 - 0x0FFF)
return value:
        0x00   - success
        others - error
*/
UCHAR L2_Set4KSRAMMode(UCHAR Mode) USING_0
{
        UCHAR tmp0;

		#if (K_CHIP_SET == K_CHIP_533)
	        tmp0 = XBYTE[0x2C00];
    	    XBYTE[0x2C00] = tmp0 & 0x1d;

	        //PRINT_L2("        L2_Set4KSRAMMode: Enter L2_Set4KSRAMMode\n");

	        if(Mode == 0)        XBYTE[0x2C11] = 0x00;                    
			else if(Mode == 1)   XBYTE[0x2C11] = 0x01;
			else if(Mode == 2)   XBYTE[0x2C11] = 0x02;
			else                {XBYTE[0x2C00] = tmp0 | 0x02; return 0x01;}
			XBYTE[0x2C00] = tmp0 | 0x02;
		#elif (K_CHIP_SET == K_CHIP_8591)
	        tmp0 = XBYTE[0x2100];
    	    XBYTE[0x2100] = tmp0 & 0x1d;

	        //PRINT_L2("        L2_Set4KSRAMMode: Enter L2_Set4KSRAMMode\n");

	        if(Mode == 0)        XBYTE[0x2111] = 0x00;                    
			else if(Mode == 1)   XBYTE[0x2111] = 0x01;
			else if(Mode == 2)   XBYTE[0x2111] = 0x02;
			else                {XBYTE[0x2100] = tmp0 | 0x02; return 0x01;}
			XBYTE[0x2100] = tmp0 | 0x02;
		#endif


        //PRINT_L2("        L2_Set4KSRAMMode: Exit L2_Set4KSRAMMode\n");

        return L2K_SUCCESS;
}
void CPUIO_PushState(void) 
{
 UCHAR i;
 USHORT index;	
  CPUIO_STATUS[0]=XBYTE[0x201A];
  CPUIO_STATUS[1]=XBYTE[0x2030];
  CPUIO_STATUS[2]=XBYTE[0x2038];
  CPUIO_STATUS[3]=XBYTE[0x20D0];
  CPUIO_STATUS[4]=XBYTE[0x2102];
  CPUIO_STATUS[5]=XBYTE[0x2103];
  CPUIO_STATUS[6]=XBYTE[0x2010];
  CPUIO_STATUS[7]=XBYTE[0x2004];
  for (i=8,index=0x2400;i<=16;i++,index++)
  CPUIO_STATUS[i]=XBYTE[index]; 

 }
void CPUIO_PopState(void) 
{
 UCHAR i;
 USHORT index;	
 XBYTE[0x201A]=CPUIO_STATUS[0];
 XBYTE[0x2030]=CPUIO_STATUS[1];
 XBYTE[0x2038]=CPUIO_STATUS[2];
 XBYTE[0x20D0]=CPUIO_STATUS[3];
 XBYTE[0x2102]=CPUIO_STATUS[4];
 XBYTE[0x2103]=CPUIO_STATUS[5];
 XBYTE[0x2010]=CPUIO_STATUS[6];
 XBYTE[0x2004]=CPUIO_STATUS[7];
 XBYTE[0x2050]=0x00;
 XBYTE[0x2058]=0x00;
 for (i=8,index=0x2400;i<=16;i++,index++)
 XBYTE[index]=CPUIO_STATUS[i];
 }