📄 l2_adsp.h
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/*
;***************************************************************************
; SUNPLUS TECHNOLOGY Co., LTD.
; MULTIMEDIA SYSTEM Div.,
; SYSTEM Dept. IV
; Sunplus Recommended Software.
;***************************************************************************
; Project Name : PA8591
; File Name : L2_ADSP.h
; Built Date : 2002/8/27
;
; Copyright 2002 Sunplus Technology Co., Ltd.
; 19, Innovation Road 1, Science-Based Industrial Park,
; Hsin-Chu, Taiwan, R.O.C.
; Email : @sunplus.com.tw
; All rights are reserved. Reproduction in whole or part is prohibited
; without the prior written consent of the copyright owner.
;
; COMPANY CONFIDENTIAL
;***************************************************************************
Revision History:
Rev Date Author
____________________________________________________________________________
1.0 2002/08/27 Chamber
Build.
*/
//--------------------------------------------------------------------------------------------
//--- For PA8591/PA8628 Application the Xdata is define the 0X33xx,
//
// patch 4.4-7@wyeo@remove debug message, begin
/*
#define CARDLIB_RELEASE 1
#define K_SLASH /
#if CARDLIB_RELEASE
#define M_Card_Printf;/K_SLASH
#else
#define M_Card_Printf printf
#endif
*/
#define DSPLIB_RELEASE 1
#define K_DLASH /
#if DSPLIB_RELEASE
#define M_DSP_Printf;/K_DLASH
#else
#define M_DSP_Printf printf
#endif
//#include "DSPdevice.h"
//------DSP EQ Type ---
#define K_EQType_NORMAL 0x00
#define K_EQType_DBB 0x01
#define K_EQType_POP 0x02
#define K_EQType_ROCK 0x03
#define K_EQType_CLASSIC 0x04
#define K_EQType_JAZZ 0x05
//--------------------------------------------------------------------------------------------
#define LDSP_SUCCESS 0x00
#define LDSP_ERROR_GENERAL 0x01
#define LDSP_ERROR_TIMEOUT 0x02
#define LDSP_ERROR_BUSY 0xFE
//--------------------------------------------------------------------------------------------
//----------------------------
#define DSP_ADLSB XBYTE[0x2E40]
#define DSP_ADMSB XBYTE[0x2E41]
#define DSP_DBusH XBYTE[0x2E44]
#define DSP_DBusM XBYTE[0x2E43]
#define DSP_DBusL XBYTE[0x2E42]
#define DSP_RWCtrl XBYTE[0x2E45]
//----------------------------
#define DSP_CMDIn XBYTE[0x2E20] //
//#define DSP_CMDInMSB XBYTE[0x2E21]
#define DSP_CMDOut XBYTE[0x2E22]
//#define DSP_CMDOutMSB XBYTE[0x2E23]
#define DSP_CMDAck XBYTE[0x2E24]
//-------------------------------
//#define EV_Chip_For_DSP
#ifdef EV_Chip_For_DSP
#define DSP_Dummy XBYTE[0x2E46]
//#define DSP_Dummy XBYTE[0x3346]
#endif
//--- Define The Register address inside DSP
//--- These Address is not directly access by MCU,but access from DSP.
#define DSP_WMACrtlReg0 0x3937 // WMA control Register
#define DSP_VersionID 0x3CF6 // Get DSP Version
#define DSP_CMDCheck 0x3CAF // DSP Command Checker for MCU, see 0x3F40
#define DSP_InAddress 0x3E00 // DSP In Buffer Address
#define DSP_FrameSizeA 0x3E01 // DSP Frame Size Address
#define DSP_OutAddress 0x3E10 // DSP Out Buffer Address
//----------- Silence detection for Audio and Voice!
#define DSP_SilenceLV 0x3E30 // DSP Silence threshold Level, default is 0x50
#define DSP_SilenceDT 0x3E31 // DSP Silence Interval Duration, default is 0x64 ,Unit:13.5mSec
#define DSP_SilenceST 0x3E32 // DSP Silence Status Flag, bit[0]:Postprocessor, bit[1]:PreProcessor!
#define DSP_DVRDelta 0x3E37 // The Voice input differential between V(n+1)-Vn(Criterion), default is 0x30
#define DSP_UnVoxCnt 0x3E38 // The Voice input amount of differential, Need to clear for DSP
#define DSP_UnVOXState 0x3E39 // The Voice input amount of differential is larger than DSP_DVRDelta. default is 0x30(Unslience)
#define DSP_VoxCnt 0x3E3A // The Voice input amount of differential, Need to clear for DSP
#define DSP_VOXState 0x3E3B // The Voice input amount of differential is larger than DSP_DVRDelta, default is 63D,(silence)
//-----------
#define DSP_InPageCnt 0x3E0B // DSP In Buffer Page Counter
#define DSP_CtrlWav 0x3E53 // Enable/Disable DSP control DVR file Header.
#define DSP_PlayDvrFrac 0x3E0C // DSP Play DVR Frame counter
#define DSP_ResBuffer 0x3E0D // DSP Residual Buffer Size
#define DSP_EncDvrFrac 0x3E50 // DSP Encode DVR Frame counter
#define DSP_ErrorFrame 0x3F51 // DSP Error FrameCnt Flag
#define DSP_RampStatus 0x3E92 // DSP audio/Speech ramp status, 1:OK, 0:not yet.
//
#define DSP_CommandST 0x3F40 // DSP Command perform status
#define DSP_CMDPayload 0x3F41 // DSP Command Payload
//
#define DSP_MPEGSt 0x3F49 // DSP MPEG Decoder Status
#define DSP_FrameCnt 0x3E24 // DSP MPEG Decoder Status
#define DSP_DVRFrameCnt 0x3E50 // DSP MPEG Decoder Status
#define DSP_MPEGst 0x3F49 // The status of MPEG
#define DSP_PFST0 0x3F50 // The Program flow Status #0
#define DSP_PFST1 0x3F51 // The Program flow Status #1
#define DSP_PFST2 0x3F52 // The Program flow Status #2
#define DSP_SilenceCtrl 0x3F53 // DSP Silence Control Register
//--Audio Control
#define DSP_AudioCtrl 0x3F55 // Audio Control
#define DSP_CMDFlg 0x3F57
#define DSP_BufferCtrl 0x3F58
#define DSP_RepeatCtrl 0x3F59
#define DSP_DPCCtrl 0x3F5D
#define DSP_PlaySkipCnt 0x3F5E // Skip Frame count for Fast Forward
#define DSP_PlayCFrCnt 0x3F5F // Play Frame Count for Fast Forward
#define DSP_ModeReady 0x3F61 // DSP Initialize Mode for Ready
//
#define DSP_IDStrAdd 0x3F70 // DSP ID String Address
#define DSP_ChipIDAdd 0x3F7D // DSP Chip ID String Address
#define DSP_CmdReady 0x3F7B // DSP Command Ready
#define DSP_WMAPageCnt 0x3F98 // DSP WMA Page Counter of random access
#define DSP_WMARndAcc 0x3F99 // DSP WMA random access flag
#define DSP_MP3BitRate 0x3FA5 // The Bit rate of current MP3 file
#define DSP_EnableCMD 0x3FBE // DSP Command Decoder Enable
//------756 Register
// decoder status registers
#define ST0_ADDR 0x3F50 // ESP mem status
#define ST1_ADDR 0x3F51 // ESP operating status
#define ST2_ADDR 0x3F52 // DRAM mem valid write
#define ST3_ADDR 0x3F53 // DRAM mem write
#define ST4_ADDR 0x3F54 // DRAM mem read
#define ST5_ADDR 0x3F55 // DRAM mem valid data counter
#define ST0_INT_MASK 0x3F4E // ST0 interrupt mask; 1: enable interrupt, 0: disable interrupt
#define ST0_STOPBO_MASK 0x3F57 // STO DRAM buffer out mask; 1: not moving from DRAM, 0: moving from DRAM
#define ST0_STOPBI_MASK 0x3F58 // STO DRAM buffer in mask; 1: not moving to DRAM, 0: moving to DRAM
//---- End of 756 Registers
//--------------------------------------------------------------------------------------------
//--- Define CommandSet between with MCU and DSP
#define DCMD_SysClkCfg 0x05 // System Phase Lock loop configuartion
#define DCMD_WMEM 0x07 // Write DSP memory mapping registers
#define DCMD_RMEM 0x0B // Read DSP memory mapping registers
#define DCMD_AudTxCfg 0x0A // Audio Interface in transmit configuration
#define DCMD_DecMode 0x0D // Decoder Mode setting
#define DCMD_VolCtrl 0x51 // Digital volume Control
#define DCMD_EqCtrl 0x59 // Equalizer Control
#define DCMD_DVRCfg 0x79 // DVR operation configuration
#define DCMD_RepCtrl 0x7D // mp3 repeater control
#define DCMD_SilCtrl 0x7F // Auto silence detection Control
//---
#define DCMD_Play 0x80 // Play
#define DCMD_ClearBuf 0x81 // Clear Buffer and Reset the Buffer Address
#define DCMD_Pause 0x84 // Pause
#define DCMD_Mute 0x88 // Mute
#define DCMD_Stop 0x8C // Stop
#define DCMD_Sleep 0x98 // Sleep
#define DCMD_AskBitrate 0xC0 // Get the bit rate of current file
#define DCMD_DatIn 0xD0 // Receive Data End
#define DCMD_DatOut 0xD4 // Transmit Data End
#define DCMD_ChkBuf 0xDC // Check the status of Buffer
#define DCMD_EOF 0xF0 // Command for EOF
#define DCMD_Reset 0xF2 // Software reset command
#define DCMD_Multiply 0xFC // DSP do multiply
//--
/**********************
* DECODER COMMAND *
**********************/
#define DECODER_SYS_CLK_CONFIG 0x05 // system clock config.
#define DECODER_RESET_CDROM_MODE 0x08 // reset cdrom mode
#define DECODER_AUD_CLK_CONFIG 0x0A // audio output clock config.
#define DECODER_DECODER_MODE 0x0D // decoder mode setting
#define DECODER_DRAM_CONFIG 0x15 // DRAM type and size config.
#define DECODER_CDDSP_CONFIG 0x22 // CD-DSP i/f config.
#define DECODER_SHOCK_FLAG_CONFIG 0x35 // shock flag config.
#define DECODER_DMAR1024 0x0b // DMA read 1024 word.
#define DECODER_DMAR16 0x0f // DMA read 16 word.
#define DECODER_DATA_COMPARE_START 0x20 // Data compare_connect start
#define DECODER_DATA_COMPARE_STOP 0x24 // Data compare_connect stop
#define DECODER_DMAR32 0x27 // DMA read 32 word.
#define DECODER_DMAW01 0x13 // DMA write 1 word.
#define DECODER_DMAW02 0x17 // DMA write 2 word.
#define DECODER_DMAW04 0x1b // DMA write 4 word.
#define DECODER_DMAW08 0x1f // DMA write 8 word.
#define DECODER_DMAW16 0x23 // DMA write 16 word.
#define DECODER_DMAW32 0x37 // DMA write 32 word.
#define DECODER_CDDA_SHOCK 0x18 // Issue the CDDA shock to SPCA756A
#define DECODER_CDFMIN 0x2B // CDFmIn indicates the first frm addr. of input data
#define DECODER_CDFMINLEN 0x30 // CDFmEnd indicates the last frm addr. of input data
#define DECODER_CDFILELEN 0x33 // Length of file(sector)
#define DECODER_DMA_TRANS_SIZE_CONFIG 0x39 // DMA transaction size config. (reserved)
#define DECODER_READ_CDFM 0x3b // reads CDROM disc data and put on internal SRAM
#define DECODER_ECC_MODE 0x3D // ECC mode setting. 1: Mode 1 disc; 0: Mode 2 disc
#define DECODER_WRITE_DM_ADDR 0x3E // set the internal SRAM write address
#define DECODER_WRITE_DM 0x42 // continuously write SRAM
#define DECODER_READ_DM_ADDR 0x4A // set the internal SRAM read address
#define DECODER_READ_DM 0x4C // continuously read SRAM
#define DECODER_VOL 0x51 // volume control
#define DECODER_SKIP_SECTOR 0x55 // skip sector
#define DECODER_EQ 0x59 // equalizer control
#define DECODER_ADPCM_COMP_CTRL 0x65 // CDDA ADPCM compression control/repeater control
#define DECODER_DATA_COMPARE_CONNECT 0x69 // CDDA data compare and connect setting
#define DECODER_DRAM_ADDR_OFST 0x6A // DRAM addr. offset from the base addr.
#define DECODER_READ_DRAM 0x6C // continuously read DRAM data
#define DECODER_WRITE_DRAM 0x6E // continuously write DRAM data
#define DECODER_DATA_ERR_CTRL 0x71 // CDROM data error control
#define DECODER_UPDATE_VWP 0x74 // update DRAM valid write pointer
#define DECODER_DVR_CONFIG 0x79 // config DVR rec/play mode
#define DECODER_REP_CONTROL 0x7D // Repeater mode control
#define DECODER_SILENCE_CTRL 0x7F // auto-silence-detection control
// Type 3 Command
#define DECODER_PLAY 0x80 // play
#define DECODER_PAUSE 0x84 // pause
#define DECODER_MUTE 0x88 // mute
#define DECODER_STOP 0x8C // stop
// Decode mode
#define DECODER_DAUDIO_MODE 0x00
#define DECODER_CDDA_ESP_MODE 0x01
#define DECODER_CDDA_BUF_MODE 0x02
#define DECODER_DVR_ENC_MODE 0x04
#define DECODER_DVR_DEC_MODE 0x05
// ST0 flags
#define ST0_SHF 0x0001
#define ST0_DBOV 0x0002
#define ST0_DBUN 0x0004
#define ST0_PEF 0x0008
#define ST0_SEF 0x0010
#define ST0_PUF 0x0020
#define ST0_HFND 0x0040
#define ST0_CRCE 0x0080
#define ST0_C3E1 0x0100
#define ST0_C3E2 0x0200
#define ST0_MSFD 0x0400
#define ST0_MUTEF 0x0800
#define ST0_DVRF 0x2000
// ST1 flags
#define ST1_IBACT 0x0001
#define ST1_DCOMP 0x0002
#define ST1_ADPEN 0x0004
#define ST1_RPEF 0x0004
#define ST1_ADPDE 0x0008
#define ST1_RPDE 0x0008
#define ST1_ENSTOP 0x0010
#define ST1_DESTOP 0x0020
#define ST1_CMPOK 0x0040
#define ST1_DSPRDY 0x0080
#define ST1_UNMUTE 0x0200
#define ST1_RPOK 0x0800
#define ST1_PSEF 0x1000
#define ST1_SILENCE 0x2000
//--------------------------------------------------------------------------------------------
/***********
* Variable *
************/
extern xdata UCHAR G_DSP_MIPSClock;
extern xdata USHORT G_Currtotalsecond; //chchang_01/17/2003
extern data BIT _G723; //@@chchang_012203
extern data BIT _WMA; //@@chchang_012803
/**********************
* FUNCTION PROTOTYPES *
**********************/
void L2_DSP_MIPSSelect(UCHAR DSP_MIPS);
UCHAR L2_DSP_setVolume(UCHAR volume);
UCHAR L2_DSP_setEQ(UCHAR EQtype);
//--
UCHAR L2_Data_MCU2DSP(UCHAR DecoderMODE);
UCHAR L2_Data_DSP2MCU(void);
//mp3;DVR time count
//void L2_DSP_CheckSongTime(BIT MP3mode, BIT ADPCMmode);
void L2_DSP_CheckSongTime(UCHAR DecoderMODE);
//void L2_DSP_CheckSongTime(void);
void L2_DSP_EncTime_SecCount(void);
ULONG L2_DSP_Multi_CMD_Get(ULONG PackageNo,BYTE ByteAddr,BYTE DurationKind); //@@chchang_012303
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