📄 iom128.h
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/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect _VECTOR(10)
#define SIG_OVERFLOW2 _VECTOR(10)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(11)
#define SIG_INPUT_CAPTURE1 _VECTOR(11)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(12)
#define SIG_OUTPUT_COMPARE1A _VECTOR(12)
/* Timer/Counter Compare Match B */
#define TIMER1_COMPB_vect _VECTOR(13)
#define SIG_OUTPUT_COMPARE1B _VECTOR(13)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(14)
#define SIG_OVERFLOW1 _VECTOR(14)
/* Timer/Counter0 Compare Match */
#define TIMER0_COMP_vect _VECTOR(15)
#define SIG_OUTPUT_COMPARE0 _VECTOR(15)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect _VECTOR(16)
#define SIG_OVERFLOW0 _VECTOR(16)
/* SPI Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(17)
#define SIG_SPI _VECTOR(17)
/* USART0, Rx Complete */
#define USART0_RX_vect _VECTOR(18)
#define SIG_USART0_RECV _VECTOR(18)
#define SIG_UART0_RECV _VECTOR(18)
/* USART0 Data Register Empty */
#define USART0_UDRE_vect _VECTOR(19)
#define SIG_USART0_DATA _VECTOR(19)
#define SIG_UART0_DATA _VECTOR(19)
/* USART0, Tx Complete */
#define USART0_TX_vect _VECTOR(20)
#define SIG_USART0_TRANS _VECTOR(20)
#define SIG_UART0_TRANS _VECTOR(20)
/* ADC Conversion Complete */
#define ADC_vect _VECTOR(21)
#define SIG_ADC _VECTOR(21)
/* EEPROM Ready */
#define EE_READY_vect _VECTOR(22)
#define SIG_EEPROM_READY _VECTOR(22)
/* Analog Comparator */
#define ANALOG_COMP_vect _VECTOR(23)
#define SIG_COMPARATOR _VECTOR(23)
/* Timer/Counter1 Compare Match C */
#define TIMER1_COMPC_vect _VECTOR(24)
#define SIG_OUTPUT_COMPARE1C _VECTOR(24)
/* Timer/Counter3 Capture Event */
#define TIMER3_CAPT_vect _VECTOR(25)
#define SIG_INPUT_CAPTURE3 _VECTOR(25)
/* Timer/Counter3 Compare Match A */
#define TIMER3_COMPA_vect _VECTOR(26)
#define SIG_OUTPUT_COMPARE3A _VECTOR(26)
/* Timer/Counter3 Compare Match B */
#define TIMER3_COMPB_vect _VECTOR(27)
#define SIG_OUTPUT_COMPARE3B _VECTOR(27)
/* Timer/Counter3 Compare Match C */
#define TIMER3_COMPC_vect _VECTOR(28)
#define SIG_OUTPUT_COMPARE3C _VECTOR(28)
/* Timer/Counter3 Overflow */
#define TIMER3_OVF_vect _VECTOR(29)
#define SIG_OVERFLOW3 _VECTOR(29)
/* USART1, Rx Complete */
#define USART1_RX_vect _VECTOR(30)
#define SIG_USART1_RECV _VECTOR(30)
#define SIG_UART1_RECV _VECTOR(30)
/* USART1, Data Register Empty */
#define USART1_UDRE_vect _VECTOR(31)
#define SIG_USART1_DATA _VECTOR(31)
#define SIG_UART1_DATA _VECTOR(31)
/* USART1, Tx Complete */
#define USART1_TX_vect _VECTOR(32)
#define SIG_USART1_TRANS _VECTOR(32)
#define SIG_UART1_TRANS _VECTOR(32)
/* 2-wire Serial Interface */
#define TWI_vect _VECTOR(33)
#define SIG_2WIRE_SERIAL _VECTOR(33)
/* Store Program Memory Read */
#define SPM_READY_vect _VECTOR(34)
#define SIG_SPM_READY _VECTOR(34)
#define _VECTORS_SIZE 140
/*
The Register Bit names are represented by their bit number (0-7).
*/
/* 2-wire Control Register - TWCR */
#define TWINT 7
#define TWEA 6
#define TWSTA 5
#define TWSTO 4
#define TWWC 3
#define TWEN 2
#define TWIE 0
/* 2-wire Address Register - TWAR */
#define TWA6 7
#define TWA5 6
#define TWA4 5
#define TWA3 4
#define TWA2 3
#define TWA1 2
#define TWA0 1
#define TWGCE 0
/* 2-wire Status Register - TWSR */
#define TWS7 7
#define TWS6 6
#define TWS5 5
#define TWS4 4
#define TWS3 3
#define TWPS1 1
#define TWPS0 0
/* External Memory Control Register A - XMCRA */
#define SRL2 6
#define SRL1 5
#define SRL0 4
#define SRW01 3
#define SRW00 2
#define SRW11 1
/* External Memory Control Register B - XMCRA */
#define XMBK 7
#define XMM2 2
#define XMM1 1
#define XMM0 0
/* XDIV Divide control register - XDIV */
#define XDIVEN 7
#define XDIV6 6
#define XDIV5 5
#define XDIV4 4
#define XDIV3 3
#define XDIV2 2
#define XDIV1 1
#define XDIV0 0
/* RAM Page Z select register - RAMPZ */
#define RAMPZ0 0
/* External Interrupt Control Register A - EICRA */
#define ISC31 7
#define ISC30 6
#define ISC21 5
#define ISC20 4
#define ISC11 3
#define ISC10 2
#define ISC01 1
#define ISC00 0
/* External Interrupt Control Register B - EICRB */
#define ISC71 7
#define ISC70 6
#define ISC61 5
#define ISC60 4
#define ISC51 3
#define ISC50 2
#define ISC41 1
#define ISC40 0
/* Store Program Memory Control Register - SPMCSR, SPMCR */
#define SPMIE 7
#define RWWSB 6
#define RWWSRE 4
#define BLBSET 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0
/* External Interrupt MaSK register - EIMSK */
#define INT7 7
#define INT6 6
#define INT5 5
#define INT4 4
#define INT3 3
#define INT2 2
#define INT1 1
#define INT0 0
/* External Interrupt Flag Register - EIFR */
#define INTF7 7
#define INTF6 6
#define INTF5 5
#define INTF4 4
#define INTF3 3
#define INTF2 2
#define INTF1 1
#define INTF0 0
/* Timer/Counter Interrupt MaSK register - TIMSK */
#define OCIE2 7
#define TOIE2 6
#define TICIE1 5
#define OCIE1A 4
#define OCIE1B 3
#define TOIE1 2
#define OCIE0 1
#define TOIE0 0
/* Timer/Counter Interrupt Flag Register - TIFR */
#define OCF2 7
#define TOV2 6
#define ICF1 5
#define OCF1A 4
#define OCF1B 3
#define TOV1 2
#define OCF0 1
#define TOV0 0
/* Extended Timer Interrupt MaSK register - ETIMSK */
#define TICIE3 5
#define OCIE3A 4
#define OCIE3B 3
#define TOIE3 2
#define OCIE3C 1
#define OCIE1C 0
/* Extended Timer Interrupt Flag Register - ETIFR */
#define ICF3 5
#define OCF3A 4
#define OCF3B 3
#define TOV3 2
#define OCF3C 1
#define OCF1C 0
/* MCU general Control Register - MCUCR */
#define SRE 7
#define SRW 6
#define SRW10 6 /* new name in datasheet (2467E-AVR-05/02) */
#define SE 5
#define SM1 4
#define SM0 3
#define SM2 2
#define IVSEL 1
#define IVCE 0
/* MCU Status Register - MCUSR, MCUCSR */
#define JTD 7
#define JTRF 4
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* Timer/Counter Control Register (generic) */
#define FOC 7
#define WGM0 6
#define COM1 5
#define COM0 4
#define WGM1 3
#define CS2 2
#define CS1 1
#define CS0 0
/* Timer/Counter 0 Control Register - TCCR0 */
#define FOC0 7
#define WGM00 6
#define COM01 5
#define COM00 4
#define WGM01 3
#define CS02 2
#define CS01 1
#define CS00 0
/* Timer/Counter 2 Control Register - TCCR2 */
#define FOC2 7
#define WGM20 6
#define COM21 5
#define COM20 4
#define WGM21 3
#define CS22 2
#define CS21 1
#define CS20 0
/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */
#define AS0 3
#define TCN0UB 2
#define OCR0UB 1
#define TCR0UB 0
/* Timer/Counter Control Register A (generic) */
#define COMA1 7
#define COMA0 6
#define COMB1 5
#define COMB0 4
#define COMC1 3
#define COMC0 2
#define WGMA1 1
#define WGMA0 0
/* Timer/Counter 1 Control and Status Register A - TCCR1A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define COM1C1 3
#define COM1C0 2
#define WGM11 1
#define WGM10 0
/* Timer/Counter 3 Control and Status Register A - TCCR3A */
#define COM3A1 7
#define COM3A0 6
#define COM3B1 5
#define COM3B0 4
#define COM3C1 3
#define COM3C0 2
#define WGM31 1
#define WGM30 0
/* Timer/Counter Control and Status Register B (generic) */
#define ICNC 7
#define ICES 6
#define WGMB3 4
#define WGMB2 3
#define CSB2 2
#define CSB1 1
#define CSB0 0
/* Timer/Counter 1 Control and Status Register B - TCCR1B */
#define ICNC1 7
#define ICES1 6
#define WGM13 4
#define WGM12 3
#define CS12 2
#define CS11 1
#define CS10 0
/* Timer/Counter 3 Control and Status Register B - TCCR3B */
#define ICNC3 7
#define ICES3 6
#define WGM33 4
#define WGM32 3
#define CS32 2
#define CS31 1
#define CS30 0
/* Timer/Counter Control Register C (generic) */
#define FOCA 7
#define FOCB 6
#define FOCC 5
/* Timer/Counter 3 Control Register C - TCCR3C */
#define FOC3A 7
#define FOC3B 6
#define FOC3C 5
/* Timer/Counter 1 Control Register C - TCCR1C */
#define FOC1A 7
#define FOC1B 6
#define FOC1C 5
/* On-chip Debug Register - OCDR */
#define IDRD 7
#define OCDR7 7
#define OCDR6 6
#define OCDR5 5
#define OCDR4 4
#define OCDR3 3
#define OCDR2 2
#define OCDR1 1
#define OCDR0 0
/* Watchdog Timer Control Register - WDTCR */
#define WDCE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/*
The ADHSM bit has been removed from all documentation,
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