chip.h

這是一個實時嵌入式作業系統 實作了MCS51 ARM等MCU

/****************************************************************************************************
 * lpc214x/chip.h
 *
 *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <[e-mail]>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name Gregory Nutt nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************************************/

#ifndef __LPC214X_CHIP_H
#define __LPC214X_CHIP_H

/****************************************************************************************************
 * Included Files
 ****************************************************************************************************/

/****************************************************************************************************
 * Definitions
 ****************************************************************************************************/

/* Memory Map ***************************************************************************************/

#define LPC214X_FLASH_BASE              0x00000000
#define LPC214X_ONCHIP_RAM_BASE         0x40000000
#define LPC214X_USBDMA_RAM_BASE         0x7fd00000
#define LPC214X_BOOT_BLOCK              0x7fffd000
#define LPC214X_EXTMEM_BASE             0x80000000
#define LPC214X_APB_BASE                0xe0000000
#define LPC214X_AHB_BASE                0xf0000000

/* Peripheral Registers ****************************************************************************/

/* Register block base addresses */

#define LPC214X_WD_BASE                 0xe0000000  /* Watchdog base address */
#define LPC214X_TMR0_BASE               0xe0004000  /* Timer 0 base address*/
#define LPC214X_TMR1_BASE               0xe0008000  /* Timer 1 base address */
#define LPC214X_UART0_BASE              0xe000c000  /* UART0 base address */
#define LPC214X_UART1_BASE              0xe0010000  /* UART1 base address */
#define LPC214X_PWM_BASE                0xe0014000  /* Pulse width modulator (PWM) base address */
#define LPC214X_I2C_BASE                0xe001C000  /* I2C base address */
#define LPC214X_SPI0_BASE               0xe0020000  /* Serial Peripheral Interface 0 (SPI0) base */
#define LPC214X_RTC_BASE                0xe0024000  /* Real Time Clock (RTC) base address */
#define LPC214X_GPIO0_BASE              0xe0028000  /* General Purpose I/O (GPIO) 0 base address */
#define LPC214X_GPIO1_BASE              0xe0028010  /* General Purpose I/O (GPIO) 0 base address */
#define LPC214X_PINSEL_BASE             0xe002c000  /* Pin function select registers */
#define LPC214X_SPI1_BASE               0xe0030000  /* Serial Peripheral Interface 1 (SPI1) base */
#define LPC214X_AD0_BASE                0xe0034000  /* Analog to Digital Converter 0 base address*/
#define LPC214X_AD1_BASE                0xe0060000  /* Analog to Digital Converter 1 base address */

#define LPC214X_SCB_BASE                0xe01fc000  /* System Control Block (SBC) base address */
#define   LPC214X_MAM_BASE              0xe01fc000  /* Memory Accelerator Module (MAM) base address */
#define   LPC214X_MEMMAP                0xe01fc040  /* Memory Mapping Control */
#define   LPC214X_PLL_BASE              0xe01fc080  /* Phase Locked Loop (PLL) base address */
#define   LPC214X_PCON_BASE             0xe01fc0c0  /* Power Control (PCON) base address */
#define   LPC214X_VPBDIV                0xe01fc100  /* VPBDIV Address */
#define   LPC214X_EXT_BASE              0xe01fc140  /* External Interrupt base address */       

#define LPC214X_EMC_BASE                0xffe00000  /* External Memory Controller (EMC) base address */
#define LPC214X_VIC_BASE                0xfffff000  /* Vectored Interrupt Controller (VIC) Base */

/* Watchdog Register Offsets */

#define LPC214X_WD_MOD_OFFSET           0x00 /* Watchdog Mode Register */
#define LPC214X_WD_TC_OFFSET            0x04 /* Watchdog Time Constant Register */
#define LPC214X_WD_FEED_OFFSET          0x08 /* Watchdog Feed Register */
#define LPC214X_WD_TV_OFFSET            0x0C /* Watchdog Time Value Register */

/* Timer 0/1 register offsets */

#define LPC214X_TMR_IR_OFFSET           0x00   /* RW:Interrupt Register */
#define LPC214X_TMR_TCR_OFFSET          0x04   /* RW: Timer Control Register */
#define LPC214X_TMR_TC_OFFSET           0x08   /* RW: Timer Counter */
#define LPC214X_TMR_PR_OFFSET           0x0c   /* RW: Prescale Register */
#define LPC214X_TMR_PC_OFFSET           0x10   /* RW: Prescale Counter Register */
#define LPC214X_TMR_MCR_OFFSET          0x14   /* RW: Match Control Register */
#define LPC214X_TMR_MR0_OFFSET          0x18   /* RW: Match Register 0 */
#define LPC214X_TMR_MR1_OFFSET          0x1c   /* RW: Match Register 1 */
#define LPC214X_TMR_MR2_OFFSET          0x20   /* RW: Match Register 2 */
#define LPC214X_TMR_MR3_OFFSET          0x24   /* RW: Match Register 3 */
#define LPC214X_TMR_CCR_OFFSET          0x28   /* RW: Capture Control Register */
#define LPC214X_TMR_CR0_OFFSET          0x2c   /* R: Capture Register 0 */
#define LPC214X_TMR_CR1_OFFSET          0x30   /* R: Capture Register 1 */
#define LPC214X_TMR_CR2_OFFSET          0x34   /* R: Capture Register 2 */
#define LPC214X_TMR_CR3_OFFSET          0x38   /* RW: Capture Register 3 */
#define LPC214X_TMR_EMR_OFFSET          0x3c   /* RW: External Match Register */

#define LPC214X_TMR_CTCR_OFFSET         0x70   /* RW: Count Control Register */

/* UART0/1 Register Offsets */

#define LPC214X_UART_RBR_OFFSET         0x00   /* R: Receive Buffer Register (DLAB=0) */
#define LPC214X_UART_THR_OFFSET         0x00   /* W: Transmit Holding Register (DLAB=0) */
#define LPC214X_UART_DLL_OFFSET         0x00   /* W: Divisor Latch Register (LSB, DLAB=1) */
#define LPC214X_UART_IER_OFFSET         0x04   /* W: Interrupt Enable Register (DLAB=0) */
#define LPC214X_UART_DLM_OFFSET         0x04   /* RW: Divisor Latch Register (MSB, DLAB=1) */
#define LPC214X_UART_IIR_OFFSET         0x08   /* R: Interrupt ID Register */
#define LPC214X_UART_FCR_OFFSET         0x08   /* W: FIFO Control Register */
#define LPC214X_UART_LCR_OFFSET         0x0c   /* RW: Line Control Register */
#define LPC214X_UART_MCR_OFFSET         0x10   /* RW: Modem Control REgister (2146/6/8 UART1 Only) */
#define LPC214X_UART_LSR_OFFSET         0x14   /* R: Scratch Pad Register */
#define LPC214X_UART_MSR_OFFSET         0x18   /* RW: MODEM Status Register (2146/6/8 UART1 Only) */
#define LPC214X_UART_SCR_OFFSET         0x1c   /* RW: Line Status Register */
#define LPC214X_UART_ACR_OFFSET         0x20   /* RW: Autobaud Control Register */
#define LPC214X_UART_FDR_OFFSET         0x28   /* RW: Fractional Divider Register */
#define LPC214X_UART_TER_OFFSET         0x30   /* RW: Transmit Enable Register */

/* PWM register offsets */

#define LPC214X_PWM_IR_OFFSET           0x00   /* Interrupt Register */
#define LPC214X_PWM_TCR_OFFSET          0x04   /* Timer Control Register */
#define LPC214X_PWM_TC_OFFSET           0x08   /* Timer Counter */
#define LPC214X_PWM_PR_OFFSET           0x0c   /* Prescale Register */
#define LPC214X_PWM_PC_OFFSET           0x10   /* Prescale Counter Register */
#define LPC214X_PWM_MCR_OFFSET          0x14   /* Match Control Register */
#define LPC214X_PWM_MR0_OFFSET          0x18   /* Match Register 0 */
#define LPC214X_PWM_MR1_OFFSET          0x1c   /* Match Register 1 */
#define LPC214X_PWM_MR2_OFFSET          0x20   /* Match Register 2 */
#define LPC214X_PWM_MR3_OFFSET          0x24   /* Match Register 3 */
#define LPC214X_PWM_MR4_OFFSET          0x40   /* Match Register 4 */
#define LPC214X_PWM_MR5_OFFSET          0x44   /* Match Register 5 */
#define LPC214X_PWM_MR6_OFFSET          0x48   /* Match Register 6 */
#define LPC214X_PWM_PCR_OFFSET          0x4c   /* Control Register */
#define LPC214X_PWM_LER_OFFSET          0x50   /* Latch Enable Register */

/* I2C register offsets */

#define LPC214X_I2C_ONSET_OFFSET        0x00   /* Control Set Register */
#define LPC214X_I2C_STAT_OFFSET         0x04   /* Status Register */
#define LPC214X_I2C_DAT_OFFSET          0x08   /* Data Register */
#define LPC214X_I2C_ADR_OFFSET          0x0c   /* Slave Address Register */
#define LPC214X_I2C_SCLH_OFFSET         0x10   /* SCL Duty Cycle Register (high half word) */
#define LPC214X_I2C_SCLL_OFFSET         0x14   /* SCL Duty Cycle Register (low half word) */
#define LPC214X_I2C_ONCLR_OFFSET        0x18   /* Control Clear Register */

/* Pin function select register offsets */

#define LPC214X_PINSEL0_OFFSET          0x00   /* Pin function select register 0 */
#define LPC214X_PINSEL1_OFFSET          0x04   /* Pin function select register 1 */
#define LPC214X_PINSEL2_OFFSET          0x14   /* Pin function select register 2 */

/* Analog to Digital (AD) Converter registger offsets */
#define LPC214X_AD_ADCR_OFFSET          0x00   /* A/D Control Register */