📄 dsp105.asm
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CLRC SXM
LDP #6
LACL TIAOL_CNT
SUB #15
BCND TIAOL1,GEQ
LACL TIAOL_CNT
ADD #1
SACL TIAOL_CNT
B TIAOL0
TIAOL1
SETC SXM
LDP #6
LACC Vout_Sum
RPT #3
SFR
LDP #6
SACL Vout_E
LACC VDC_SUM
RPT #3
SFR
LDP #5
SUB VZ
; SFR
LDP #6
SACL VDC_E
LACL #0
SACL TIAOL_CNT
SACL Vout_Sum
SACL VDC_SUM
B TIAOL0
TIAOL5
ZERORLY_OFF
TIAOL0
LDP #4
CLRC SXM
LACC Iinv,10
SACH Iinv
LACL Iinv
LDP #5
SUB VZ
LDP #4
SACL Iinv
SQRA Iinv
ZALH CURRENT_H0
ADDS CURRENT_L0
APAC
SACL CURRENT_L0
SACH CURRENT_H0
LDP #4
LACC Ii,10
SACH Ii
SQRA Ii
LDP #6
ZALH ICURRENT_H0
ADDS ICURRENT_L0
APAC
SACL ICURRENT_L0
SACH ICURRENT_H0
LDP #4
ZALH WATT_H0
ADDS WATT_L0
BIT RUN_FLAG,BIT0
BCND SQUARE10,TC
LT Vout
B SQUARE20
SQUARE10
LT Vi
SQUARE20
MPY Iinv
APAC
LDP #4
SACL WATT_L0
SACH WATT_H0
LACL LNAD_DT0
ADD #1
SACL LNAD_DT0
LACL INVAD_DT0
ADD #1
SACL INVAD_DT0
SETC SXM
LDP #4
; BIT RUN_FLAG1,BIT4
; BCND SQUARE_40,NTC
; BIT RUN_FLAG1,BIT3 ;INV DELAY
; BCND SQUARE_40,TC
; BIT RUN_FLAG,BIT5 ;INV SOFT
; BCND SQUARE_40,TCBIT
; BIT RUN_FLAG,BIT7 ;DC SOFT
; BCND SQUARE_40,TC
BIT RUN_FLAG,BIT1 ;只在市电模式检测掉电。lyl
BCND SQUARE_40,NTC
SQUARE_25
;市电掉电检测
LACC Vi
LDP #5
ABS
ADD ViSUM
SACL ViSUM
LDP #5
LACL ViAD_CNT
ADD #1
SACL ViAD_CNT
SUB #20
BCND SQUARE_32,LEQ
LDP #5
LACL ViSUM
SUB #650 ;50Vrms
BCND SQUARE_30,GT
LDP #4
SBIT1 RUN_FLAG1,B2_MSK
CALL S_INVTOBAT
SQUARE_30
LDP #5
LACL #0
SACL ViSUM
SACL ViAD_CNT
SQUARE_32
LDP #4
; BIT RUN_FLAG,BIT1
; BCND SQUARE_40,NTC
; LACL LNAD_DT
; SFR
; LDP #6
; SACL QUARTE
; LDP #4
LACC Vi
LDP #6
; ABS
ADD ViSUM1
SACL ViSUM1
; LACL ViAD_CNT1
; ADD #1
; SACL ViAD_CNT1
; SUB QUARTE
; BCND SQUARE_40,LEQ
; LDP #6
; LACL ViSUM1
; SUB #4500 ;90Vrms2673,100VrmS,2970,110Vrms,3265,,133Vrms,6000
; BCND SQUARE_35,GT
; LDP #4
; CALL S_INVTOBAT
;SQUARE_35
; LDP #6
; LACL #0
; SACL ViSUM1
; SACL ViAD_CNT1
SQUARE_40
LDP #4 ;市电掉电检测
BIT RUN_FLAG1,BIT4 ;UPS在旁路模式且PFC运行时检测市电
BCND SQUARE_60,TC
BIT RUN_FLAG1,BIT0
BCND SQUARE_60,NTC
LACC Vi
LDP #5
ABS
ADD ViSUM
SACL ViSUM
LDP #5
LACL ViAD_CNT
ADD #1
SACL ViAD_CNT
SUB #20
BCND SQUARE_60,LEQ
LDP #5
LACL ViSUM
SUB #650 ;50Vrms
BCND SQUARE_50,GT
LDP #4
SBIT1 RUN_FLAG1,B2_MSK
CALL S_BYPASACT
SQUARE_50
LDP #5
LACL #0
SACL ViSUM
SACL ViAD_CNT
SQUARE_60
LDP #4
LACC Vi
ABS
LDP #5
SACL Viold
SQUARE_END
LDP #4 ;短路检测
BIT RUN_FLAG,BIT0
BCND SHORT_CHK10,TC
LDP #224
LACL XINT1
AND #40H
LDP #6
ADD SHORT_CNT
SACL SHORT_CNT
SHORT_CHK10
CLRC SXM
LDP #5
ADC_BUSY21
LAR AR3,#ADCTRL1
BIT *,BIT7
CALL S_ADCHK
BCND ADC_BUSY21,TC
SPLK #0,ADCHK_CNT
LDP #5
ADC_BUSY22
BLDD #ADCFIFO1,V1
LAR AR3,#ADCTRL2
LACC *
AND #0018H
BCND ADC_BUSY22,NEQ
ADC_BUSY23
BLDD #ADCFIFO2,VZ1
LACC *
AND #00C0H
BCND ADC_BUSY23,NEQ
GPT1_UEND
LAR AR3,#ADCTRL1
LDP #4
LACC AD_CNT
BCND ADC_START1,EQ
SUB #1
BCND ADC_START2,EQ
SUB #1
BCND GPT1_END,EQ
B ADC_START3
ADC_START1
SPLK #1111100111001001B,* ;sample Tsink(CH4) and VBAT(CH12)
B GPT1_END
ADC_START2
SPLK #1111100111011011B,* ;sample VBUS+(CH5),VBUS-(ch13)
B GPT1_END
ADC_START3
SPLK #1111100110100101B,* ;sample Vi(CH2) and Ii(CH10)
GPT1_END
LDP #6
LACL ADCHK_BAD
SUB #2
BCND GISR2_END,LT
LDP #4
SBIT1 LOAD_FLAG,B9_MSK ;A/D FAIL
SBIT1 FAULT_FLAG,B15_MSK
CALL S_BYPASACT
GISR2_END
LDP #6
SPLK #0,ADCHK_BAD
SETC INTM
POP_ALL
CLRC INTM
RET
;=====================================================================
SPWM_GEN:
SETC SXM
LDP #4
LACC M_PARA
; SPLK #819,M_PARA
; LT SIN_VAL ;Q15
; MPY M_PARA ;Q10
; MPY SIN_AMP ;01-6-4 10:29
; PAC
; SACH GPR0,6
; LT GPR0
; MPY #250 ;Ts/4
; PAC
; SACH GPR0,1
; LACC GPR0
NEG
ADD #250
LDP #232
SACL CMPR1
LACL #230
SACL CMPR2
LDP #6
LACL FAN_SPEED
; LACC #480
LDP #232
SACL CMPR3
RET
XISR2:
PUSH_ALL
LDP #4
SBIT1 FAULT_FLAG,B8_MSK
SBIT1 FAULT_FLAG,B15_MSK
CALL S_BYPASACT
SETC INTM
POP_ALL
CLRC INTM
RET
;=====================================================================
; I S R - PHANTOM
;
; Description: Dummy ISR, used to trap spurious interrupts.
;
; Modifies: Nothing
;
; Last Update: 16 June 95
;=====================================================================
PHANTOM KICK_DOG ;Resets WD counter
B PHANTOM
;-------------------------------------------------------------------------
INITV_PI:
LDP #5 ; Variables data page
SPLK #9,Kvp ; set yv PI proportionnal parameter Q9 12
SPLK #90,Kvi ; set yv PI integral parameter Q12 120
SPLK #1400H,Kvsat ; set yv PI saturation parameter Q12 5120
SPLK #230,Kvd ; Q9 280 250
SPLK #0,xv_high ; clear yv PI integral term
SPLK #0,xv_low
RET
;********************************************************************
;Subroutine: PI module
;inputs:yv,yvref
;outputs: NEW_M
;********************************************************************
V_PID:
SETC SXM ; Sign extension mode
SETC OVM ; Overflow mode
SPM 0 ; SPM set for Q15 multiplication
; yv_error = yvref - yv
LDP #5 ; Variables data page
LACC yvref ; ACC = yvref Q6
ADD yv ; ACC = yvref - yv Q6
SACL yv_error ; yv_error = yvref - yv Q6
; upi = x + yv_error * Kvp
LACC xv_high,9 ; Q15
LT yv_error ; TREG = yv_error
MPY Kvp ; PREG = yv_error * Kvp P=Q6*Q9
APAC ; ACC high = xv_high + yv_error * Kvp Q15
RPT #6
NORM *
sach upi_temp ;Q6
lacc yv_error ;Q6
sub yv_error0 ;Q6
sacl xv_low ;Q6
lt xv_low
mpy Kvd ;Q9
pac
rpt #6
norm * ;Q22
sach xv_low ;Q6
lacc xv_low ;Q6
add upi_temp ;Q6
RPT #5
SFR
sacl upi ;Q0
; SACH upi ;upi = xv_high + yv_error * Kvp Q0
LACC upi
SUB #max_U
BCND SAT_POSS,GEQ
LACC upi
SUB #min_U
BCND SAT_NEGG,LEQ
LACC upi
B NEXTT
SAT_POSS
LACC #max_U
B NEXTT
SAT_NEGG
LACC #min_U
NEXTT
LDP #4
SACL NEW_M
LDP #5
; satv = Ud - upi
SUB upi
SACL satv
; x = x + error * Kvi + satv * Kvsat
; x: 32 bits (x= xv_low + xv_high)
LT satv ;TREG = satv Q0
MPY Kvsat ;PREG = satv * Kvsat Q12
PAC ;ACC = satv * Kvsat Q12
RPT #5
SFL
LT yv_error ;TREG = yv_error Q6
MPY Kvi ;PREG = yv_error * Kvi Q12
APAC ;ACC = satv*Kvsat + yv_error*Kvi Q18
ADD xv_high,12 ;Q18
RPT #3
NORM * ;Q22
SACH xv_high ;Q6
lacc yv_error
sacl yv_error0
RET
;****************************************************************************
;Subroutine Name：SINWAVE_GEN Function:Generate ref sine wave of inverter
;INPUT:RAMP_STEP,TETA_H,TETA_L,
;OUTPUT：yvref
;Designer:Yu Hongquan LastUpdate:21/7/2000
;============================================================================
SINWAVE_GEN
SETC SXM
LDP #4
; SPLK #VOUT_REF,GPR2
; LT GPR2 ;Q6
; splk #0B65H,SIN_AMP ;5ab2h 0BB2
LT SIN_AMP ;Q6
MPY SIN_VAL ;Q15
PAC
RPT #14
SFR
LDP #5
SACL yvref ;Q0
RET
;=====================================================================
;ISR - CAP1&CAP2 INT
;Description:计算输入/输出电压的频率，并根据频率差和相位差完成锁相计算。
;
;Temporary register:GPR4
;
;=====================================================================
CAPINT PUSH_ALL
LDP #232
LACC EVIVRC
LDP #4
SACL GPR0
SUB #33H ;Line_zero INT Vector
BCND CAP1_INT,EQ
LACL GPR0
SUB #34H ;INV_Zero INT Vector
BCND CAP2_INT,EQ
B PHANTOM
CAP1_INT ;Line_zero INT
; LDP #232 ;CAL Line Frequency
CLRC SXM
CAP1X
; LACL CAP1FIFO ;TEST CAPFIFO
; LDP #4
; SACL NEW1_CNT
LDP #4
BLDD #CAP1FIFO,NEW1_CNT ;test0, lyl
MAR *,AR5
LAR AR5,#CAPFIFO
LACC *
AND #0300H
BCND CAP1X,NEQ
LACL NEW1_CNT
SUB OLD1_CNT
BCND CAP1_1,GEQ
ADD #0FFFFH
ADD #1
CAP1_1 SACL LINEF
SUB #6B6H ;0C35/20*11(90HZ)
BCND CAP14,LT
; LDP #6
; LACC ViSUM1
; SUB #2000
; BCND CAP14,GT
; LACC ViSUM1
; ADD #2000
; BCND CAP15,LT
; LDP #6
; SPLK #0,ViSUM1
LDP #5
LACL T50USCNT
SACL LINE_NEW
SUB LINE_OLD
BCND CAP1_2,GEQ
ADD #0FFFFH
ADD #1
CAP1_2
SACL LINE_POINT
DMOV LINE_NEW
LDP #4
DMOV LINV_L0
DMOV LINV_H0
DMOV LNAD_DT0
LACL #0
SACL LINV_L0
SACL LINV_H0
SACL LNAD_DT0
BIT RUN_FLAG,BIT0
BCND CAP1_2A,NTC
DMOV WATT_L0
DMOV WATT_H0
DMOV CURRENT_L0
DMOV CURRENT_H0
LDP #4
LACL #0
SACL WATT_L0
SACL WATT_H0
SACL CURRENT_L0
SACL CURRENT_H0
CAP1_2A
BIT LOAD_FLAG,BIT11 ;判断是否做转电池动作
BCND CAP1_3,NTC
ACSCR_OFF
DCSCR_ON
CON_DC
LDP #4
SBIT0 LOAD_FLAG,B11_MSK ;清除市电转电池模式标志
SBIT1 RUN_FLAG,B9_MSK ;SET FREE RUN FLAG
; SBIT0 PHASE_FLAG,B2_MSK ;Clear PLL going Flag
SBIT0 PHASE_FLAG,B3_MSK ;Clear PLL OK Flag
CAP1_3
LDP #4
LACL NEW1_CNT
SACL OLD1_CNT
SPLK #0,LINEZERO
LACL LINEVOLTV
SUB #7
BCND CAP1_5,LEQ
SBIT0 ERR_FLAG,B8_MSK
CAP1_5
LDP #4
; BIT RUN_FLAG,BIT4
; BCND CAP13,NTC
; SBIT0 RUN_FLAG,B4_MSK
; STS_BYP
; LDP #225
; SBIT0 PCDATDIR,B2_MSK ;Set IOPC2=0,IOPC3=0
; SBIT0 PCDATDIR,B3_MSK
CAP13
CALL S_FLTLINEF
B CAP_END
CAP14
LDP #4
LACL OLD1_CNT
SACL NEW1_CNT
B CAP_END
CAP15
LDP #4
DMOV NEW1_CNT
LDP #6
SPLK #0,ViSUM1
B CAP_END
CAP2_INT ;INV_Zero INT
; LDP #232 ;CAL INV Frequency
CLRC SXM
CAP2X
LDP #4
BLDD #CAP2FIFO,NEW2_CNT ;test0, lyl
MAR *,AR5
LAR AR5,#CAPFIFO
LACC *
AND #0C00H
BCND CAP2X,NEQ
LACL NEW2_CNT
; LACL CAP2FIFO
; LDP #4
; SACL NEW2_CNT
SUB OLD2_CNT
BCND CAP2_1,GT
ADD #0FFFFH
ADD #1
CAP2_1 SACL INV_TM
LDP #4
LACL NEW2_CNT
SACL OLD2_CNT
SPLK #0,INVZERO
; B CAP_END
DMOV INVV_L0
DMOV INVV_H0
DMOV INVAD_DT0
LACL #0
SACL INVV_L0
SACL INVV_H0
SACL INVAD_DT0
BIT RUN_FLAG,BIT0
BCND CAP2_3,TC
DMOV WATT_L0
DMOV WATT_H0
DMOV CURRENT_L0
DMOV CURRENT_H0
LACL #0
SACL WATT_L0
SACL WATT_H0
SACL CURRENT_L0
SACL CURRENT_H0
LDP #6
DMOV ICURRENT_L0
DMOV ICURRENT_H0
SACL ICURRENT_L0
SACL ICURRENT_H0
LDP #4
CAP2_3
LACL SIN_POINTER
ADD #1536
AND #07FFH
LDP #5
SACL LINEZERO_POINT3
LDP #4
BIT PHASE_FLAG,BIT9
BCND REGINVF26,NTC
; STS_LIN
; LDP #225
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