📄 adc.lis
字号:
.module adc.c
.area text(rom, con, rel)
0000 .dbfile E:\TWINTI~1\adc.c
0000 .dbfunc e adc_int _adc_int fV
.even
0000 _adc_int::
0000 .dbline -1
0000 .dbline 29
0000 ;
0000 ; /********************************************************************************/
0000 ; //
0000 ; // builder : 2007-04-10
0000 ; // Target : ATMEAG 48V
0000 ; // Crystal : 内部 8.00 MHz
0000 ; //
0000 ; // ADC 转换模块
0000 ;
0000 ; /********************************************************************************/
0000 ;
0000 ; #include <iom48v.h>
0000 ; #include <macros.h>
0000 ;
0000 ; #define uchar unsigned char
0000 ; #define uint unsigned int
0000 ;
0000 ; #define CH0 0x40
0000 ; #define CH1 0x41
0000 ; #define CH2 0x42
0000 ; #define CH3 0x43
0000 ; #define CH4 0x44
0000 ; #define CH5 0x45
0000 ; #define CH6 0x46
0000 ; #define CH7 0x47
0000 ;
0000 ;
0000 ; void adc_int(void)
0000 ; {
0000 .dbline 30
0000 ; ADMUX = 0x40; //set adc power avcc and the ref is Avref
0000 80E4 ldi R24,64
0002 80937C00 sts 124,R24
0006 .dbline 31
0006 ; ADCSRA = 0xC2; //enable adc and the div parame is 8
0006 82EC ldi R24,194
0008 80937A00 sts 122,R24
000C .dbline -2
000C L1:
000C .dbline 0 ; func end
000C 0895 ret
000E .dbend
000E .dbfunc e adc_colect _adc_colect fi
000E ; adh -> R20,R21
000E ; ad_add -> R22,R23
000E ; temp1 -> R12,R13
000E ; i -> R10
000E ; temp -> R14,R15
000E ; chanal -> R16
.even
000E _adc_colect::
000E 00D0 rcall push_gset5
0010 .dbline -1
0010 .dbline 40
0010 ; }
0010 ;
0010 ;
0010 ; /*---------------------------------------------------------------
0010 ; ADC
0010 ; ----------------------------------------------------------------*/
0010 ;
0010 ; uint adc_colect(uchar chanal)
0010 ; {
0010 .dbline 46
0010 ; uchar i;
0010 ; uint ad_add;
0010 ; uint temp,temp1;
0010 ; uint adh;
0010 ;
0010 ; if(chanal==0) ADMUX = CH0;
0010 0023 tst R16
0012 21F4 brne L3
0014 .dbline 46
0014 80E4 ldi R24,64
0016 80937C00 sts 124,R24
001A 29C0 rjmp L4
001C L3:
001C .dbline 47
001C ; else if(chanal==1) ADMUX = CH1;
001C 0130 cpi R16,1
001E 21F4 brne L5
0020 .dbline 47
0020 81E4 ldi R24,65
0022 80937C00 sts 124,R24
0026 23C0 rjmp L6
0028 L5:
0028 .dbline 48
0028 ; else if(chanal==2) ADMUX = CH2;
0028 0230 cpi R16,2
002A 21F4 brne L7
002C .dbline 48
002C 82E4 ldi R24,66
002E 80937C00 sts 124,R24
0032 1DC0 rjmp L8
0034 L7:
0034 .dbline 49
0034 ; else if(chanal==3) ADMUX = CH3;
0034 0330 cpi R16,3
0036 21F4 brne L9
0038 .dbline 49
0038 83E4 ldi R24,67
003A 80937C00 sts 124,R24
003E 17C0 rjmp L10
0040 L9:
0040 .dbline 50
0040 ; else if(chanal==4) ADMUX = CH4;
0040 0430 cpi R16,4
0042 21F4 brne L11
0044 .dbline 50
0044 84E4 ldi R24,68
0046 80937C00 sts 124,R24
004A 11C0 rjmp L12
004C L11:
004C .dbline 51
004C ; else if(chanal==5) ADMUX = CH5;
004C 0530 cpi R16,5
004E 21F4 brne L13
0050 .dbline 51
0050 85E4 ldi R24,69
0052 80937C00 sts 124,R24
0056 0BC0 rjmp L14
0058 L13:
0058 .dbline 52
0058 ; else if(chanal==6) ADMUX = CH6;
0058 0630 cpi R16,6
005A 21F4 brne L15
005C .dbline 52
005C 86E4 ldi R24,70
005E 80937C00 sts 124,R24
0062 05C0 rjmp L16
0064 L15:
0064 .dbline 53
0064 ; else if(chanal==7) ADMUX = CH7;
0064 0730 cpi R16,7
0066 19F4 brne L17
0068 .dbline 53
0068 87E4 ldi R24,71
006A 80937C00 sts 124,R24
006E L17:
006E L16:
006E L14:
006E L12:
006E L10:
006E L8:
006E L6:
006E L4:
006E .dbline 55
006E ;
006E ; ad_add = 0;
006E 6627 clr R22
0070 7727 clr R23
0072 .dbline 57
0072 ;
0072 ; for(i=0;i<8;i++)
0072 AA24 clr R10
0074 22C0 rjmp L22
0076 L19:
0076 .dbline 58
0076 ; {
0076 .dbline 59
0076 ; ADCSRA = ADCSRA|(1<<ADSC); //start the adc
0076 80917A00 lds R24,122
007A 8064 ori R24,64
007C 80937A00 sts 122,R24
0080 L23:
0080 .dbline 60
0080 L24:
0080 .dbline 60
0080 ; while(ADCSRA&(1<<ADSC)); //wait for the adc finish
0080 20907A00 lds R2,122
0084 26FC sbrc R2,6
0086 FCCF rjmp L23
0088 .dbline 62
0088 ;
0088 ; ADCSRA = ADCSRA|(1<<ADSC); //start the adc
0088 80917A00 lds R24,122
008C 8064 ori R24,64
008E 80937A00 sts 122,R24
0092 L26:
0092 .dbline 63
0092 L27:
0092 .dbline 63
0092 20907A00 lds R2,122
0096 26FC sbrc R2,6
0098 FCCF rjmp L26
009A .dbline 65
009A C0907800 lds R12,120
009E DD24 clr R13
00A0 .dbline 66
00A0 80917900 lds R24,121
00A4 9927 clr R25
00A6 8370 andi R24,3
00A8 9070 andi R25,0
00AA 7C01 movw R14,R24
00AC FE2C mov R15,R14
00AE EE24 clr R14
00B0 .dbline 67
00B0 EC0C add R14,R12
00B2 FD1C adc R15,R13
00B4 .dbline 68
00B4 6E0D add R22,R14
00B6 7F1D adc R23,R15
00B8 .dbline 69
00B8 L20:
00B8 .dbline 57
00B8 A394 inc R10
00BA L22:
00BA .dbline 57
00BA 8A2D mov R24,R10
00BC 8830 cpi R24,8
00BE D8F2 brlo L19
00C0 .dbline 70
00C0 ; while(ADCSRA&(1<<ADSC)); //wait for the adc finish
00C0 ;
00C0 ; temp1 = ADCL;
00C0 ; temp = (ADCH&0x03)<<8;
00C0 ; temp += temp1;
00C0 ; ad_add += temp;
00C0 ; }
00C0 ; adh = ad_add>>3;
00C0 AB01 movw R20,R22
00C2 5695 lsr R21
00C4 4795 ror R20
00C6 5695 lsr R21
00C8 4795 ror R20
00CA 5695 lsr R21
00CC 4795 ror R20
00CE .dbline 71
00CE ; return(adh);
00CE 8A01 movw R16,R20
00D0 .dbline -2
00D0 L2:
00D0 00D0 rcall pop_gset5
00D2 .dbline 0 ; func end
00D2 0895 ret
00D4 .dbsym r adh 20 i
00D4 .dbsym r ad_add 22 i
00D4 .dbsym r temp1 12 i
00D4 .dbsym r i 10 c
00D4 .dbsym r temp 14 i
00D4 .dbsym r chanal 16 c
00D4 .dbend
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