adc.s

前两年在一家模型公司开发的

	.module adc.c
	.area text(rom, con, rel)
	.dbfile E:\TWINTI~1\adc.c
	.dbfunc e adc_int _adc_int fV
	.even
_adc_int::
	.dbline -1
	.dbline 29
; 
; /********************************************************************************/
; //		
; // 		builder : 2007-04-10
; // 		Target  : ATMEAG 48V
; // 		Crystal : 内部 8.00 MHz
; //
; //		ADC 转换模块
; 		
; /********************************************************************************/
; 
; #include 	<iom48v.h>
; #include 	<macros.h>
; 
; #define		uchar	unsigned char
; #define		uint	unsigned int
; 
; #define 	CH0		0x40
; #define		CH1		0x41
; #define		CH2		0x42
; #define 	CH3     0x43
; #define 	CH4		0x44
; #define		CH5		0x45
; #define		CH6		0x46
; #define 	CH7     0x47
; 
; 
; void adc_int(void)
; {
	.dbline 30
; 	 ADMUX	= 0x40;		//set adc power avcc and the ref is Avref
	ldi R24,64
	sts 124,R24
	.dbline 31
;  	 ADCSRA	= 0xC2; 	//enable adc and the div parame is 8	 
	ldi R24,194
	sts 122,R24
	.dbline -2
L1:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e adc_colect _adc_colect fi
;            adh -> R20,R21
;         ad_add -> R22,R23
;          temp1 -> R12,R13
;              i -> R10
;           temp -> R14,R15
;         chanal -> R16
	.even
_adc_colect::
	rcall push_gset5
	.dbline -1
	.dbline 40
; }
; 
; 
; /*---------------------------------------------------------------
;    			ADC 
; ----------------------------------------------------------------*/
; 
; uint adc_colect(uchar chanal)
; {
	.dbline 46
;  	uchar i;
; 	uint  ad_add;
; 	uint  temp,temp1;
; 	uint  adh;
; 	
; 	if(chanal==0)  		ADMUX = CH0;
	tst R16
	brne L3
	.dbline 46
	ldi R24,64
	sts 124,R24
	rjmp L4
L3:
	.dbline 47
; 	else if(chanal==1)	ADMUX = CH1;
	cpi R16,1
	brne L5
	.dbline 47
	ldi R24,65
	sts 124,R24
	rjmp L6
L5:
	.dbline 48
; 	else if(chanal==2)	ADMUX = CH2;
	cpi R16,2
	brne L7
	.dbline 48
	ldi R24,66
	sts 124,R24
	rjmp L8
L7:
	.dbline 49
; 	else if(chanal==3)	ADMUX = CH3;
	cpi R16,3
	brne L9
	.dbline 49
	ldi R24,67
	sts 124,R24
	rjmp L10
L9:
	.dbline 50
; 	else if(chanal==4)	ADMUX = CH4;
	cpi R16,4
	brne L11
	.dbline 50
	ldi R24,68
	sts 124,R24
	rjmp L12
L11:
	.dbline 51
; 	else if(chanal==5)	ADMUX = CH5;
	cpi R16,5
	brne L13
	.dbline 51
	ldi R24,69
	sts 124,R24
	rjmp L14
L13:
	.dbline 52
; 	else if(chanal==6)	ADMUX = CH6;
	cpi R16,6
	brne L15
	.dbline 52
	ldi R24,70
	sts 124,R24
	rjmp L16
L15:
	.dbline 53
; 	else if(chanal==7)	ADMUX = CH7;
	cpi R16,7
	brne L17
	.dbline 53
	ldi R24,71
	sts 124,R24
L17:
L16:
L14:
L12:
L10:
L8:
L6:
L4:
	.dbline 55
; 	
; 	ad_add = 0;
	clr R22
	clr R23
	.dbline 57
; 	
; 	for(i=0;i<8;i++)
	clr R10
	rjmp L22
L19:
	.dbline 58
; 	{
	.dbline 59
;  		ADCSRA = ADCSRA|(1<<ADSC);			   //start the adc
	lds R24,122
	ori R24,64
	sts 122,R24
L23:
	.dbline 60
L24:
	.dbline 60
; 		while(ADCSRA&(1<<ADSC));			   //wait for the adc finish
	lds R2,122
	sbrc R2,6
	rjmp L23
	.dbline 62
;  		
;  		ADCSRA = ADCSRA|(1<<ADSC);			   //start the adc
	lds R24,122
	ori R24,64
	sts 122,R24
L26:
	.dbline 63
L27:
	.dbline 63
	lds R2,122
	sbrc R2,6
	rjmp L26
	.dbline 65
	lds R12,120
	clr R13
	.dbline 66
	lds R24,121
	clr R25
	andi R24,3
	andi R25,0
	movw R14,R24
	mov R15,R14
	clr R14
	.dbline 67
	add R14,R12
	adc R15,R13
	.dbline 68
	add R22,R14
	adc R23,R15
	.dbline 69
L20:
	.dbline 57
	inc R10
L22:
	.dbline 57
	mov R24,R10
	cpi R24,8
	brlo L19
	.dbline 70
; 		while(ADCSRA&(1<<ADSC));			   //wait for the adc finish
; 		
; 		temp1 = ADCL;
; 		temp  = (ADCH&0x03)<<8;
; 		temp   += temp1;
; 		ad_add += temp;                                                                      
; 	}
; 	adh = ad_add>>3;
	movw R20,R22
	lsr R21
	ror R20
	lsr R21
	ror R20
	lsr R21
	ror R20
	.dbline 71
; 	return(adh);
	movw R16,R20
	.dbline -2
L2:
	rcall pop_gset5
	.dbline 0 ; func end
	ret
	.dbsym r adh 20 i
	.dbsym r ad_add 22 i
	.dbsym r temp1 12 i
	.dbsym r i 10 c
	.dbsym r temp 14 i
	.dbsym r chanal 16 c
	.dbend