initialize.s

与GPS模块连接

	.module initialize.c
	.area text(rom, con, rel)
	.dbfile E:\RXTest\initialize.c
	.dbfunc e timer0_init _timer0_init fV
	.even
_timer0_init::
	.dbline -1
	.dbline 15
; #define Initialize_C 
; 
; #include "allheads.h"
; 
; /*void timer0_init(void)
; { 
;  TCCR0A=0x00;
; TCCR0B=0x03;
; TCNT0=0x83;
; OCR0A=0x00;
; OCR0B=0x00;
; }*/
; 
; void timer0_init(void) 
; {     TCCR0B = 0x00; //stop 
	.dbline 15
	clr R2
	out 0x25,R2
	.dbline 16
;          TCNT0  = Txd_Bit_Delay;//0xD0; //set count 
	ldi R24,152
	out 0x26,R24
	.dbline 17
;          TCCR0A = 0x00;  
	out 0x24,R2
	.dbline -2
L9:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e timer2_init _timer2_init fV
	.even
_timer2_init::
	.dbline -1
	.dbline 24
; } 
; //TIMER2 initialize - prescale:1024
; // WGM: Normal
; // desired value: 20mSec
; // actual value: 19.968mSec (0.2%)
; void timer2_init(void)
; {
	.dbline 25
;   TCCR2B = 0x00; //stop
	clr R2
	sts 177,R2
	.dbline 26
;  ASSR  = 0x00; //set async mode
	sts 182,R2
	.dbline 27
;  TCNT2 = 0x83; //setup
	ldi R24,131
	sts 178,R24
	.dbline 28
;  OCR2A = 0x7D;
	ldi R24,125
	sts 179,R24
	.dbline 29
;  OCR2B = 0x00;
	sts 180,R2
	.dbline 30
;  TCCR2A = 0x00; 
	sts 176,R2
	.dbline 31
;  TCCR2B = 0x04; //start
	ldi R24,4
	sts 177,R24
	.dbline -2
L10:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e initialize _initialize fV
	.even
_initialize::
	.dbline -1
	.dbline 35
; }
; 
; void initialize(void)
; {
	.dbline 38
; // Crystal Oscillator division factor: 1
; //#pragma optsize-
; asm("cli");//CLI(); 
	cli
	.dbline 39
; CLKPR=0x80;
	ldi R24,128
	sts 97,R24
	.dbline 40
; CLKPR=0x00;
	clr R2
	sts 97,R2
	.dbline 45
; //#ifdef _OPTIMIZE_SIZE_
; //#pragma optsize+
; //#endif
; 
; PORTB=0xFF;
	ldi R24,255
	out 0x5,R24
	.dbline 46
; DDRB=0xFF;
	out 0x4,R24
	.dbline 48
; 
; PORTC=0xF7;
	ldi R24,247
	out 0x8,R24
	.dbline 49
; DDRC=0xf7;//ef;//0xF7;
	out 0x7,R24
	.dbline 51
; 
; PORTD=0x60;
	ldi R24,96
	out 0xb,R24
	.dbline 52
; DDRD=0x9C;
	ldi R24,156
	out 0xa,R24
	.dbline 63
;  //TCCR0B = 0x00; //stop
;  //TCNT0 = 0x83; //set count
;  //TCCR0A = 0x00; 
;  //TCCR0B = 0x03; //start time
; /*
; TCCR0A=0x00;
; TCCR0B=0x03;
; TCNT0=0x06;
; OCR0A=0x00;
; OCR0B=0x00;*/
; UCSR0B = 0x00; //disable while setting baud rate
	sts 193,R2
	.dbline 64
;  UCSR0A = 0x00;
	sts 192,R2
	.dbline 65
;  UCSR0C = 0x06;
	ldi R24,6
	sts 194,R24
	.dbline 66
;  UBRR0L = 0x67;//33;//0xCF; //set baud rate lo
	ldi R24,103
	sts 196,R24
	.dbline 67
;  UBRR0H = 0x00; //set baud rate hi
	sts 197,R2
	.dbline 68
;  UCSR0B =0x98;// 0x18;//0x90
	ldi R24,152
	sts 193,R24
	.dbline 70
;  
; TCCR1A=0x00;
	sts 128,R2
	.dbline 71
; TCCR1B=0x00;
	sts 129,R2
	.dbline 72
; TCNT1H=0x00;
	sts 133,R2
	.dbline 73
; TCNT1L=0x00;
	sts 132,R2
	.dbline 74
; ICR1H=0x00;
	sts 135,R2
	.dbline 75
; ICR1L=0x00;
	sts 134,R2
	.dbline 76
; OCR1AH=0x00;
	sts 137,R2
	.dbline 77
; OCR1AL=0x00;
	sts 136,R2
	.dbline 78
; OCR1BH=0x00;
	sts 139,R2
	.dbline 79
; OCR1BL=0x00;
	sts 138,R2
	.dbline 81
; 
;  timer0_init();
	rcall _timer0_init
	.dbline 82
;  timer2_init();
	rcall _timer2_init
	.dbline 83
; TCCR2B = 0x00; //stop
	clr R2
	sts 177,R2
	.dbline 84
;  ASSR  = 0x00; //set async mode
	sts 182,R2
	.dbline 85
;  TCNT2 = 0x83; //setup
	ldi R24,131
	sts 178,R24
	.dbline 86
;  OCR2A = 0x7D;
	ldi R24,125
	sts 179,R24
	.dbline 87
;  OCR2B = 0x00;
	sts 180,R2
	.dbline 88
;  TCCR2A = 0x00; 
	sts 176,R2
	.dbline 89
;  TCCR2B = 0x04; //start
	ldi R24,4
	sts 177,R24
	.dbline 91
; 
; EICRA=0x00;
	sts 105,R2
	.dbline 92
; EIMSK=0x00;
	out 0x1d,R2
	.dbline 93
; PCICR=0x00;
	sts 104,R2
	.dbline 96
; 
; // Timer/Counter 0 Interrupt(s) initialization
; TIMSK0=0x00;
	sts 110,R2
	.dbline 98
; // Timer/Counter 1 Interrupt(s) initialization
; TIMSK1=0x00;
	sts 111,R2
	.dbline 101
; // Timer/Counter 2 Interrupt(s) initialization
; //TIMSK2=0x00;
; TIMSK2 = 0x01; 
	ldi R24,1
	sts 112,R24
	.dbline 105
; // Analog Comparator initialization
; // Analog Comparator: Off
; // Analog Comparator Input Capture by Timer/Counter 1: Off
; ACSR=0x80;
	ldi R24,128
	out 0x30,R24
	.dbline 106
; ADCSRB=0x00;
	sts 123,R2
	.dbline 109
; // Global enable interrupts
; //#asm("sei")
; asm("sei");// SEI(); 
	sei
	.dbline -2
L11:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e delay_ms _delay_ms fV
;              a -> R20
;              b -> R22
;              i -> R16
	.even
_delay_ms::
	rcall push_gset2
	.dbline -1
	.dbline 112
; }
; 
; void delay_ms(uchar i) {
	.dbline 114
	ldi R20,1
	rjmp L16
L13:
	.dbline 114
; 	uchar a, b;
; 	for (a = 1; a < i; a++) {
	.dbline 115
	ldi R22,1
	rjmp L20
L17:
	.dbline 115
	.dbline 115
	.dbline 115
L18:
	.dbline 115
	inc R22
L20:
	.dbline 115
	tst R22
	brne L17
	.dbline 116
L14:
	.dbline 114
	inc R20
L16:
	.dbline 114
	cp R20,R16
	brlo L13
	.dbline -2
L12:
	rcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym r a 20 c
	.dbsym r b 22 c
	.dbsym r i 16 c
	.dbend
	.dbfunc e Delay _Delay fV
;         _Delay -> R16,R17
	.even
_Delay::
	.dbline -1
	.dbline 119
; 		for (b = 1; b; b++) {;}
; 		}
; }
; 
; void Delay(uint _Delay){
L22:
	.dbline 120
	.dbline 120
	.dbline 120
L23:
	.dbline 120
; 	while(--_Delay){;}
	movw R24,R16
	sbiw R24,1
	movw R16,R24
	cpi R16,0
	cpc R16,R17
	brne L22
X0:
	.dbline -2
L21:
	.dbline 0 ; func end
	ret
	.dbsym r _Delay 16 i
	.dbend
	.dbfunc e DelayLong _DelayLong fV
;              i -> R20,R21
;              j -> R22,R23
;          value -> R16,R17
	.even
_DelayLong::
	rcall push_gset2
	.dbline -1
	.dbline 123
; }
; 
; void DelayLong(uint value){
	.dbline 125
	clr R20
	clr R21
	rjmp L29
L26:
	.dbline 125
; uint i,j;
; for(i=0;i<value;i++){
	.dbline 126
	clr R22
	clr R23
	rjmp L33
L30:
	.dbline 126
	.dbline 126
	.dbline 126
L31:
	.dbline 126
	subi R22,255  ; offset = 1
	sbci R23,255
L33:
	.dbline 126
	cpi R22,255
	ldi R30,0
	cpc R23,R30
	brlo L30
	.dbline 127
L27:
	.dbline 125
	subi R20,255  ; offset = 1
	sbci R21,255
L29:
	.dbline 125
	cp R20,R16
	cpc R21,R17
	brlo L26
	.dbline -2
L25:
	rcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym r i 20 i
	.dbsym r j 22 i
	.dbsym r value 16 i
	.dbend