dec2812.tan.qmsg

DSP2812开发板板上的CPLD源代码

{ "Info" "ITDB_TH_RESULT" "74273:inst\|12 D\[7\] WR 4.914 ns register " "Info: th for register \"74273:inst\|12\" (data pin = \"D\[7\]\", clock pin = \"WR\") is 4.914 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR destination 9.177 ns + Longest register " "Info: + Longest clock path from clock \"WR\" to destination register is 9.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns WR 1 CLK PIN_96 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_96; Fanout = 5; CLK Node = 'WR'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { WR } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 208 88 256 224 "WR" "" } { 1696 792 824 1712 "WR" "" } { 1904 104 136 1920 "WR" "" } { 1904 368 400 1920 "WR" "" } { 1904 792 824 1920 "WR" "" } { 1440 560 592 1456 "WR" "" } { 2120 904 936 2136 "WR" "" } { 2344 120 200 2360 "WR" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.253 ns) + CELL(0.740 ns) 4.125 ns inst50~22 2 COMB LC_X2_Y3_N8 3 " "Info: 2: + IC(2.253 ns) + CELL(0.740 ns) = 4.125 ns; Loc. = LC_X2_Y3_N8; Fanout = 3; COMB Node = 'inst50~22'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "2.993 ns" { WR inst50~22 } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1888 872 936 1936 "inst50" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.200 ns) 5.070 ns inst39 3 COMB LC_X2_Y3_N0 8 " "Info: 3: + IC(0.745 ns) + CELL(0.200 ns) = 5.070 ns; Loc. = LC_X2_Y3_N0; Fanout = 8; COMB Node = 'inst39'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "0.945 ns" { inst50~22 inst39 } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1680 872 936 1728 "inst39" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.189 ns) + CELL(0.918 ns) 9.177 ns 74273:inst\|12 4 REG LC_X7_Y4_N8 1 " "Info: 4: + IC(3.189 ns) + CELL(0.918 ns) = 9.177 ns; Loc. = LC_X7_Y4_N8; Fanout = 1; REG Node = '74273:inst\|12'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "4.107 ns" { inst39 74273:inst|12 } "NODE_NAME" } "" } } { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { 888 320 384 968 "12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.990 ns ( 32.58 % ) " "Info: Total cell delay = 2.990 ns ( 32.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.187 ns ( 67.42 % ) " "Info: Total interconnect delay = 6.187 ns ( 67.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "9.177 ns" { WR inst50~22 inst39 74273:inst|12 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "9.177 ns" { WR WR~combout inst50~22 inst39 74273:inst|12 } { 0.000ns 0.000ns 2.253ns 0.745ns 3.189ns } { 0.000ns 1.132ns 0.740ns 0.200ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { 888 320 384 968 "12" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.484 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns D\[7\] 1 PIN PIN_6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_6; Fanout = 1; PIN Node = 'D\[7\]'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { D[7] } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns D~0 2 COMB IOC_X1_Y3_N0 2 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X1_Y3_N0; Fanout = 2; COMB Node = 'D~0'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "1.132 ns" { D[7] D~0 } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.072 ns) + CELL(0.280 ns) 4.484 ns 74273:inst\|12 3 REG LC_X7_Y4_N8 1 " "Info: 3: + IC(3.072 ns) + CELL(0.280 ns) = 4.484 ns; Loc. = LC_X7_Y4_N8; Fanout = 1; REG Node = '74273:inst\|12'" {  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "3.352 ns" { D~0 74273:inst|12 } "NODE_NAME" } "" } } { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { 888 320 384 968 "12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 31.49 % ) " "Info: Total cell delay = 1.412 ns ( 31.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.072 ns ( 68.51 % ) " "Info: Total interconnect delay = 3.072 ns ( 68.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "4.484 ns" { D[7] D~0 74273:inst|12 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "4.484 ns" { D[7] D~0 74273:inst|12 } { 0.000ns 0.000ns 3.072ns } { 0.000ns 1.132ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "9.177 ns" { WR inst50~22 inst39 74273:inst|12 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "9.177 ns" { WR WR~combout inst50~22 inst39 74273:inst|12 } { 0.000ns 0.000ns 2.253ns 0.745ns 3.189ns } { 0.000ns 1.132ns 0.740ns 0.200ns 0.918ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "4.484 ns" { D[7] D~0 74273:inst|12 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "4.484 ns" { D[7] D~0 74273:inst|12 } { 0.000ns 0.000ns 3.072ns } { 0.000ns 1.132ns 0.280ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 26 16:59:52 2007 " "Info: Processing ended: Thu Jul 26 16:59:52 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}