📄 dec2812.tan.qmsg
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{ "Info" "ITAN_NO_REG2REG_EXIST" "A\[12\] " "Info: No valid register-to-register data paths exist for clock \"A\[12\]\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "A\[11\] " "Info: No valid register-to-register data paths exist for clock \"A\[11\]\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "74273:inst22\|19 D\[0\] A\[11\] -0.800 ns register " "Info: tsu for register \"74273:inst22\|19\" (data pin = \"D\[0\]\", clock pin = \"A\[11\]\") is -0.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.748 ns + Longest pin register " "Info: + Longest pin to register delay is 3.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns D\[0\] 1 PIN PIN_99 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_99; Fanout = 1; PIN Node = 'D\[0\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { D[0] } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns D~7 2 COMB IOC_X2_Y5_N1 6 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X2_Y5_N1; Fanout = 6; COMB Node = 'D~7'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "1.132 ns" { D[0] D~7 } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.336 ns) + CELL(0.280 ns) 3.748 ns 74273:inst22\|19 3 REG LC_X2_Y3_N7 1 " "Info: 3: + IC(2.336 ns) + CELL(0.280 ns) = 3.748 ns; Loc. = LC_X2_Y3_N7; Fanout = 1; REG Node = '74273:inst22\|19'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "2.616 ns" { D~7 74273:inst22|19 } "NODE_NAME" } "" } } { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { 48 320 384 128 "19" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 37.67 % ) " "Info: Total cell delay = 1.412 ns ( 37.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.336 ns ( 62.33 % ) " "Info: Total interconnect delay = 2.336 ns ( 62.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "3.748 ns" { D[0] D~7 74273:inst22|19 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.748 ns" { D[0] D~7 74273:inst22|19 } { 0.000ns 0.000ns 2.336ns } { 0.000ns 1.132ns 0.280ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { 48 320 384 128 "19" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "A\[11\] destination 4.881 ns - Shortest register " "Info: - Shortest clock path from clock \"A\[11\]\" to destination register is 4.881 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns A\[11\] 1 CLK PIN_12 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'A\[11\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { A[11] } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 456 88 256 472 "A\[12..9\]" "" } { 944 96 129 960 "A\[12\]" "" } { 960 96 184 976 "A\[10\]" "" } { 976 96 184 992 "A\[11\]" "" } { 992 96 184 1008 "A\[9\]" "" } { 1192 96 184 1208 "A\[9\]" "" } { 1176 96 136 1192 "A\[10\]" "" } { 1160 96 136 1176 "A\[11\]" "" } { 1144 96 184 1160 "A\[12\]" "" } { 1392 96 184 1408 "A\[9\]" "" } { 1344 96 136 1360 "A\[12\]" "" } { 1360 96 184 1376 "A\[11\]" "" } { 1376 96 184 1392 "A\[10\]" "" } { 1560 360 448 1576 "A\[12\]" "" } { 1608 360 400 1624 "A\[9\]" "" } { 1560 792 872 1576 "A\[12\]" "" } { 1576 792 872 1592 "A\[11\]" "" } { 1592 792 872 1608 "A\[10\]" "" } { 1608 792 872 1624 "A\[9\]" "" } { 1768 104 184 1784 "A\[12\]" "" } { 1784 104 184 1800 "A\[11\]" "" } { 1800 104 184 1816 "A\[10\]" "" } { 1816 104 136 1832 "A\[9\]" "" } { 1768 368 448 1784 "A\[12\]" "" } { 1784 368 448 1800 "A\[11\]" "" } { 1816 368 448 1832 "A\[9\]" "" } { 1608 96 184 1624 "A\[9\]" "" } { 1560 96 184 1576 "A\[12\]" "" } { 1576 96 136 1592 "A\[11\]" "" } { 1800 368 401 1816 "A\[10\]" "" } { 1768 792 825 1784 "A\[12\]" "" } { 1784 792 825 1800 "A\[11\]" "" } { 1800 792 872 1816 "A\[10\]" "" } { 1816 792 872 1832 "A\[9\]" "" } { 1304 560 640 1320 "A\[12\]" "" } { 1336 560 640 1352 "A\[10\]" "" } { 1352 560 640 1368 "A\[9\]" "" } { 1320 560 593 1336 "A\[11\]" "" } { 1592 360 448 1608 "A\[10\]" "" } { 1576 360 400 1592 "A\[11\]" "" } { 1592 96 136 1608 "A\[10\]" "" } { 1256 792 825 1272 "A\[11\]" "" } { 1288 792 872 1304 "A\[9\]" "" } { 1240 792 872 1256 "A\[12\]" "" } { 1272 792 872 1288 "A\[10\]" "" } { 1416 792 872 1432 "A\[11\]" "" } { 1400 792 825 1416 "A\[12\]" "" } { 1432 792 825 1448 "A\[10\]" "" } { 1448 792 872 1464 "A\[9\]" "" } { 1984 904 984 2000 "A\[12\]" "" } { 2000 904 984 2016 "A\[11\]" "" } { 2032 904 984 2048 "A\[9\]" "" } { 2016 904 937 2032 "A\[10\]" "" } { 2208 200 280 2224 "A\[12\]" "" } { 2224 200 280 2240 "A\[11\]" "" } { 2240 120 224 2256 "A\[10\]" "" } { 2256 120 168 2272 "A\[9\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(0.740 ns) 3.284 ns inst62 2 COMB LC_X2_Y3_N3 3 " "Info: 2: + IC(1.381 ns) + CELL(0.740 ns) = 3.284 ns; Loc. = LC_X2_Y3_N3; Fanout = 3; COMB Node = 'inst62'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "2.121 ns" { A[11] inst62 } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 2104 984 1048 2152 "inst62" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.679 ns) + CELL(0.918 ns) 4.881 ns 74273:inst22\|19 3 REG LC_X2_Y3_N7 1 " "Info: 3: + IC(0.679 ns) + CELL(0.918 ns) = 4.881 ns; Loc. = LC_X2_Y3_N7; Fanout = 1; REG Node = '74273:inst22\|19'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "1.597 ns" { inst62 74273:inst22|19 } "NODE_NAME" } "" } } { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { 48 320 384 128 "19" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.821 ns ( 57.80 % ) " "Info: Total cell delay = 2.821 ns ( 57.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.060 ns ( 42.20 % ) " "Info: Total interconnect delay = 2.060 ns ( 42.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "4.881 ns" { A[11] inst62 74273:inst22|19 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "4.881 ns" { A[11] A[11]~combout inst62 74273:inst22|19 } { 0.000ns 0.000ns 1.381ns 0.679ns } { 0.000ns 1.163ns 0.740ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "3.748 ns" { D[0] D~7 74273:inst22|19 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "3.748 ns" { D[0] D~7 74273:inst22|19 } { 0.000ns 0.000ns 2.336ns } { 0.000ns 1.132ns 0.280ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "4.881 ns" { A[11] inst62 74273:inst22|19 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "4.881 ns" { A[11] A[11]~combout inst62 74273:inst22|19 } { 0.000ns 0.000ns 1.381ns 0.679ns } { 0.000ns 1.163ns 0.740ns 0.918ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "WR CE\[0\] 74273:inst7\|18 14.717 ns register " "Info: tco from clock \"WR\" to destination pin \"CE\[0\]\" through register \"74273:inst7\|18\" is 14.717 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR source 8.563 ns + Longest register " "Info: + Longest clock path from clock \"WR\" to source register is 8.563 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns WR 1 CLK PIN_96 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_96; Fanout = 5; CLK Node = 'WR'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { WR } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 208 88 256 224 "WR" "" } { 1696 792 824 1712 "WR" "" } { 1904 104 136 1920 "WR" "" } { 1904 368 400 1920 "WR" "" } { 1904 792 824 1920 "WR" "" } { 1440 560 592 1456 "WR" "" } { 2120 904 936 2136 "WR" "" } { 2344 120 200 2360 "WR" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.253 ns) + CELL(0.740 ns) 4.125 ns inst50~22 2 COMB LC_X2_Y3_N8 3 " "Info: 2: + IC(2.253 ns) + CELL(0.740 ns) = 4.125 ns; Loc. = LC_X2_Y3_N8; Fanout = 3; COMB Node = 'inst50~22'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "2.993 ns" { WR inst50~22 } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1888 872 936 1936 "inst50" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.742 ns) + CELL(0.200 ns) 5.067 ns inst50 3 COMB LC_X2_Y3_N4 3 " "Info: 3: + IC(0.742 ns) + CELL(0.200 ns) = 5.067 ns; Loc. = LC_X2_Y3_N4; Fanout = 3; COMB Node = 'inst50'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "0.942 ns" { inst50~22 inst50 } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1888 872 936 1936 "inst50" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.578 ns) + CELL(0.918 ns) 8.563 ns 74273:inst7\|18 4 REG LC_X7_Y1_N4 4 " "Info: 4: + IC(2.578 ns) + CELL(0.918 ns) = 8.563 ns; Loc. = LC_X7_Y1_N4; Fanout = 4; REG Node = '74273:inst7\|18'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "3.496 ns" { inst50 74273:inst7|18 } "NODE_NAME" } "" } } { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { 168 320 384 248 "18" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.990 ns ( 34.92 % ) " "Info: Total cell delay = 2.990 ns ( 34.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.573 ns ( 65.08 % ) " "Info: Total interconnect delay = 5.573 ns ( 65.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "8.563 ns" { WR inst50~22 inst50 74273:inst7|18 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.563 ns" { WR WR~combout inst50~22 inst50 74273:inst7|18 } { 0.000ns 0.000ns 2.253ns 0.742ns 2.578ns } { 0.000ns 1.132ns 0.740ns 0.200ns 0.918ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { 168 320 384 248 "18" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.778 ns + Longest register pin " "Info: + Longest register to pin delay is 5.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74273:inst7\|18 1 REG LC_X7_Y1_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N4; Fanout = 4; REG Node = '74273:inst7\|18'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { 74273:inst7|18 } "NODE_NAME" } "" } } { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { 168 320 384 248 "18" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.511 ns) 1.497 ns 74138:inst10\|15 2 COMB LC_X7_Y1_N5 1 " "Info: 2: + IC(0.986 ns) + CELL(0.511 ns) = 1.497 ns; Loc. = LC_X7_Y1_N5; Fanout = 1; COMB Node = '74138:inst10\|15'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "1.497 ns" { 74273:inst7|18 74138:inst10|15 } "NODE_NAME" } "" } } { "74138.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74138.bdf" { { 16 568 632 88 "15" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.959 ns) + CELL(2.322 ns) 5.778 ns CE\[0\] 3 PIN PIN_57 0 " "Info: 3: + IC(1.959 ns) + CELL(2.322 ns) = 5.778 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'CE\[0\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "4.281 ns" { 74138:inst10|15 CE[0] } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1120 808 984 1136 "CE\[3..0\]" "" } { 808 920 956 824 "CE\[0\]" "" } { 824 920 956 840 "CE\[1\]" "" } { 840 920 956 856 "CE\[2\]" "" } { 856 920 956 872 "CE\[3\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.833 ns ( 49.03 % ) " "Info: Total cell delay = 2.833 ns ( 49.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.945 ns ( 50.97 % ) " "Info: Total interconnect delay = 2.945 ns ( 50.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "5.778 ns" { 74273:inst7|18 74138:inst10|15 CE[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "5.778 ns" { 74273:inst7|18 74138:inst10|15 CE[0] } { 0.000ns 0.986ns 1.959ns } { 0.000ns 0.511ns 2.322ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "8.563 ns" { WR inst50~22 inst50 74273:inst7|18 } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "8.563 ns" { WR WR~combout inst50~22 inst50 74273:inst7|18 } { 0.000ns 0.000ns 2.253ns 0.742ns 2.578ns } { 0.000ns 1.132ns 0.740ns 0.200ns 0.918ns } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "5.778 ns" { 74273:inst7|18 74138:inst10|15 CE[0] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "5.778 ns" { 74273:inst7|18 74138:inst10|15 CE[0] } { 0.000ns 0.986ns 1.959ns } { 0.000ns 0.511ns 2.322ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A\[11\] D\[1\] 12.021 ns Longest " "Info: Longest tpd from source pin \"A\[11\]\" to destination pin \"D\[1\]\" is 12.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns A\[11\] 1 CLK PIN_12 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'A\[11\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { A[11] } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 456 88 256 472 "A\[12..9\]" "" } { 944 96 129 960 "A\[12\]" "" } { 960 96 184 976 "A\[10\]" "" } { 976 96 184 992 "A\[11\]" "" } { 992 96 184 1008 "A\[9\]" "" } { 1192 96 184 1208 "A\[9\]" "" } { 1176 96 136 1192 "A\[10\]" "" } { 1160 96 136 1176 "A\[11\]" "" } { 1144 96 184 1160 "A\[12\]" "" } { 1392 96 184 1408 "A\[9\]" "" } { 1344 96 136 1360 "A\[12\]" "" } { 1360 96 184 1376 "A\[11\]" "" } { 1376 96 184 1392 "A\[10\]" "" } { 1560 360 448 1576 "A\[12\]" "" } { 1608 360 400 1624 "A\[9\]" "" } { 1560 792 872 1576 "A\[12\]" "" } { 1576 792 872 1592 "A\[11\]" "" } { 1592 792 872 1608 "A\[10\]" "" } { 1608 792 872 1624 "A\[9\]" "" } { 1768 104 184 1784 "A\[12\]" "" } { 1784 104 184 1800 "A\[11\]" "" } { 1800 104 184 1816 "A\[10\]" "" } { 1816 104 136 1832 "A\[9\]" "" } { 1768 368 448 1784 "A\[12\]" "" } { 1784 368 448 1800 "A\[11\]" "" } { 1816 368 448 1832 "A\[9\]" "" } { 1608 96 184 1624 "A\[9\]" "" } { 1560 96 184 1576 "A\[12\]" "" } { 1576 96 136 1592 "A\[11\]" "" } { 1800 368 401 1816 "A\[10\]" "" } { 1768 792 825 1784 "A\[12\]" "" } { 1784 792 825 1800 "A\[11\]" "" } { 1800 792 872 1816 "A\[10\]" "" } { 1816 792 872 1832 "A\[9\]" "" } { 1304 560 640 1320 "A\[12\]" "" } { 1336 560 640 1352 "A\[10\]" "" } { 1352 560 640 1368 "A\[9\]" "" } { 1320 560 593 1336 "A\[11\]" "" } { 1592 360 448 1608 "A\[10\]" "" } { 1576 360 400 1592 "A\[11\]" "" } { 1592 96 136 1608 "A\[10\]" "" } { 1256 792 825 1272 "A\[11\]" "" } { 1288 792 872 1304 "A\[9\]" "" } { 1240 792 872 1256 "A\[12\]" "" } { 1272 792 872 1288 "A\[10\]" "" } { 1416 792 872 1432 "A\[11\]" "" } { 1400 792 825 1416 "A\[12\]" "" } { 1432 792 825 1448 "A\[10\]" "" } { 1448 792 872 1464 "A\[9\]" "" } { 1984 904 984 2000 "A\[12\]" "" } { 2000 904 984 2016 "A\[11\]" "" } { 2032 904 984 2048 "A\[9\]" "" } { 2016 904 937 2032 "A\[10\]" "" } { 2208 200 280 2224 "A\[12\]" "" } { 2224 200 280 2240 "A\[11\]" "" } { 2240 120 224 2256 "A\[10\]" "" } { 2256 120 168 2272 "A\[9\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.128 ns) + CELL(0.914 ns) 5.205 ns inst76~27 2 COMB LC_X2_Y2_N5 3 " "Info: 2: + IC(3.128 ns) + CELL(0.914 ns) = 5.205 ns; Loc. = LC_X2_Y2_N5; Fanout = 3; COMB Node = 'inst76~27'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "4.042 ns" { A[11] inst76~27 } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1264 184 248 1312 "inst76" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.511 ns) 6.500 ns inst77 3 COMB LC_X2_Y2_N1 2 " "Info: 3: + IC(0.784 ns) + CELL(0.511 ns) = 6.500 ns; Loc. = LC_X2_Y2_N1; Fanout = 2; COMB Node = 'inst77'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "1.295 ns" { inst76~27 inst77 } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1464 184 248 1512 "inst77" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.043 ns) + CELL(0.511 ns) 9.054 ns 74244:inst13\|6~120 4 COMB LC_X2_Y4_N1 1 " "Info: 4: + IC(2.043 ns) + CELL(0.511 ns) = 9.054 ns; Loc. = LC_X2_Y4_N1; Fanout = 1; COMB Node = '74244:inst13\|6~120'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "2.554 ns" { inst77 74244:inst13|6~120 } "NODE_NAME" } "" } } { "74244.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { { 112 296 344 144 "6" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.645 ns) + CELL(2.322 ns) 12.021 ns D\[1\] 5 PIN PIN_100 0 " "Info: 5: + IC(0.645 ns) + CELL(2.322 ns) = 12.021 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'D\[1\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "2.967 ns" { 74244:inst13|6~120 D[1] } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.421 ns ( 45.10 % ) " "Info: Total cell delay = 5.421 ns ( 45.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.600 ns ( 54.90 % ) " "Info: Total interconnect delay = 6.600 ns ( 54.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "12.021 ns" { A[11] inst76~27 inst77 74244:inst13|6~120 D[1] } "NODE_NAME" } "" } } { "f:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus51/bin/Technology_Viewer.qrui" "12.021 ns" { A[11] A[11]~combout inst76~27 inst77 74244:inst13|6~120 D[1] } { 0.000ns 0.000ns 3.128ns 0.784ns 2.043ns 0.645ns } { 0.000ns 1.163ns 0.914ns 0.511ns 0.511ns 2.322ns } } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
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