dec2812.map.eqn

DSP2812开发板板上的CPLD源代码

-- Copyright (C) 1991-2005 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B1_19 is 74273:inst2|19
--operation mode is normal

B1_19_lut_out = A1L34;
B1_19 = DFFEAS(B1_19_lut_out, inst46, VCC, , , , , , );


--B1_18 is 74273:inst2|18
--operation mode is normal

B1_18_lut_out = A1L33;
B1_18 = DFFEAS(B1_18_lut_out, inst46, VCC, , , , , , );


--B1_17 is 74273:inst2|17
--operation mode is normal

B1_17_lut_out = A1L32;
B1_17 = DFFEAS(B1_17_lut_out, inst46, VCC, , , , , , );


--B1_16 is 74273:inst2|16
--operation mode is normal

B1_16_lut_out = A1L31;
B1_16 = DFFEAS(B1_16_lut_out, inst46, VCC, , , , , , );


--B1_15 is 74273:inst2|15
--operation mode is normal

B1_15_lut_out = A1L30;
B1_15 = DFFEAS(B1_15_lut_out, inst46, VCC, , , , , , );


--B1_14 is 74273:inst2|14
--operation mode is normal

B1_14_lut_out = A1L29;
B1_14 = DFFEAS(B1_14_lut_out, inst46, VCC, , , , , , );


--B1_13 is 74273:inst2|13
--operation mode is normal

B1_13_lut_out = A1L28;
B1_13 = DFFEAS(B1_13_lut_out, inst46, VCC, , , , , , );


--A1L61 is inst69~22
--operation mode is normal

A1L61 = EXINT[5] & EXINT[3] & EXINT[2] & EXINT[1];


--B2_19 is 74273:inst11|19
--operation mode is normal

B2_19_lut_out = A1L34;
B2_19 = DFFEAS(B2_19_lut_out, inst55, VCC, , , , , , );


--inst64 is inst64
--operation mode is normal

inst64 = A1L61 & EXINT[4] # !B2_19;


--A1L60 is inst68~14
--operation mode is normal

A1L60 = B2_19 & (USBINT # 8019INT);


--B3_19 is 74273:inst7|19
--operation mode is normal

B3_19_lut_out = A1L34;
B3_19 = DFFEAS(B3_19_lut_out, inst50, VCC, , , , , , );


--A1L75 is inst84~16
--operation mode is normal

A1L75 = A[12] & (!A[11] & !CS1);


--inst84 is inst84
--operation mode is normal

inst84 = A[9] # !A[10] # !A1L75;


--inst83 is inst83
--operation mode is normal

inst83 = !A[9] # !A[10] # !A1L75;


--inst71 is inst71
--operation mode is normal

inst71 = NMI[0] & NMI[1] # !B2_19;


--B4_19 is 74273:inst22|19
--operation mode is normal

B4_19_lut_out = A1L34;
B4_19 = DFFEAS(B4_19_lut_out, inst62, VCC, , , , , , );


--B4_18 is 74273:inst22|18
--operation mode is normal

B4_18_lut_out = A1L33;
B4_18 = DFFEAS(B4_18_lut_out, inst62, VCC, , , , , , );


--B4_17 is 74273:inst22|17
--operation mode is normal

B4_17_lut_out = A1L32;
B4_17 = DFFEAS(B4_17_lut_out, inst62, VCC, , , , , , );


--A1L63 is inst73~28
--operation mode is normal

A1L63 = A[11] & A[12] & (!WR # !RD);


--A1L64 is inst73~29
--operation mode is normal

A1L64 = !A[10] & !A[9];


--B3_18 is 74273:inst7|18
--operation mode is normal

B3_18_lut_out = A1L33;
B3_18 = DFFEAS(B3_18_lut_out, inst50, VCC, , , , , , );


--B3_17 is 74273:inst7|17
--operation mode is normal

B3_17_lut_out = A1L32;
B3_17 = DFFEAS(B3_17_lut_out, inst50, VCC, , , , , , );


--D1L2 is 74138:inst10|17~33
--operation mode is normal

D1L2 = B3_18 & B3_17;


--D1L3 is 74138:inst10|17~34
--operation mode is normal

D1L3 = B3_17 & (!B3_18);


--D1L4 is 74138:inst10|17~35
--operation mode is normal

D1L4 = B3_18 & (!B3_17);


--D1_15 is 74138:inst10|15
--operation mode is normal

D1_15 = B3_18 # B3_17;


--B5_12 is 74273:inst1|12
--operation mode is normal

B5_12_lut_out = A1L27;
B5_12 = DFFEAS(B5_12_lut_out, inst42, VCC, , , , , , );


--B5_13 is 74273:inst1|13
--operation mode is normal

B5_13_lut_out = A1L28;
B5_13 = DFFEAS(B5_13_lut_out, inst42, VCC, , , , , , );


--B5_14 is 74273:inst1|14
--operation mode is normal

B5_14_lut_out = A1L29;
B5_14 = DFFEAS(B5_14_lut_out, inst42, VCC, , , , , , );


--B5_15 is 74273:inst1|15
--operation mode is normal

B5_15_lut_out = A1L30;
B5_15 = DFFEAS(B5_15_lut_out, inst42, VCC, , , , , , );


--B5_16 is 74273:inst1|16
--operation mode is normal

B5_16_lut_out = A1L31;
B5_16 = DFFEAS(B5_16_lut_out, inst42, VCC, , , , , , );


--B5_17 is 74273:inst1|17
--operation mode is normal

B5_17_lut_out = A1L32;
B5_17 = DFFEAS(B5_17_lut_out, inst42, VCC, , , , , , );


--B5_18 is 74273:inst1|18
--operation mode is normal

B5_18_lut_out = A1L33;
B5_18 = DFFEAS(B5_18_lut_out, inst42, VCC, , , , , , );


--B5_19 is 74273:inst1|19
--operation mode is normal

B5_19_lut_out = A1L34;
B5_19 = DFFEAS(B5_19_lut_out, inst42, VCC, , , , , , );


--B6_12 is 74273:inst|12
--operation mode is normal

B6_12_lut_out = A1L27;
B6_12 = DFFEAS(B6_12_lut_out, inst39, VCC, , , , , , );


--B6_13 is 74273:inst|13
--operation mode is normal

B6_13_lut_out = A1L28;
B6_13 = DFFEAS(B6_13_lut_out, inst39, VCC, , , , , , );


--B6_14 is 74273:inst|14
--operation mode is normal

B6_14_lut_out = A1L29;
B6_14 = DFFEAS(B6_14_lut_out, inst39, VCC, , , , , , );


--B6_15 is 74273:inst|15
--operation mode is normal

B6_15_lut_out = A1L30;
B6_15 = DFFEAS(B6_15_lut_out, inst39, VCC, , , , , , );


--B6_16 is 74273:inst|16
--operation mode is normal

B6_16_lut_out = A1L31;
B6_16 = DFFEAS(B6_16_lut_out, inst39, VCC, , , , , , );


--B6_17 is 74273:inst|17
--operation mode is normal

B6_17_lut_out = A1L32;
B6_17 = DFFEAS(B6_17_lut_out, inst39, VCC, , , , , , );


--B6_18 is 74273:inst|18
--operation mode is normal

B6_18_lut_out = A1L33;
B6_18 = DFFEAS(B6_18_lut_out, inst39, VCC, , , , , , );


--B6_19 is 74273:inst|19
--operation mode is normal

B6_19_lut_out = A1L34;
B6_19 = DFFEAS(B6_19_lut_out, inst39, VCC, , , , , , );


--A1L55 is inst50~22
--operation mode is normal

A1L55 = !A[11] & !A[12] & !WR;


--inst46 is inst46
--operation mode is normal

inst46 = !A[9] & (A[10] & A1L55);


--inst55 is inst55
--operation mode is normal

inst55 = !A[12] & !WR & A[11] & A1L64;


--inst50 is inst50
--operation mode is normal

inst50 = A[10] & A[9] & A1L55;


--A1L58 is inst62~17
--operation mode is normal

A1L58 = A[9] & (!A[10]);


--inst62 is inst62
--operation mode is normal

inst62 = A[11] & A[12] & A1L58 & !WR;


--A1L67 is inst75~56
--operation mode is normal

A1L67 = A[11] & !A[12] & !CS1 & !RD;


--C5L1 is 74244:inst12|26~9
--operation mode is normal

C5L1 = A[9] # INP[8] # !A1L67 # !A[10];


--A1L69 is inst76~27
--operation mode is normal

A1L69 = A[12] & !A[11] & !CS1 & !RD;


--C6L10 is 74244:inst13|26~42
--operation mode is normal

C6L10 = A[10] & A1L67 # !A[10] & (A1L69 # A1L67 & A[9]);


--C5L2 is 74244:inst12|27~9
--operation mode is normal

C5L2 = A[9] # INP[7] # !A1L67 # !A[10];


--C5L3 is 74244:inst12|31~9
--operation mode is normal

C5L3 = A[9] # INP[6] # !A1L67 # !A[10];


--inst75 is inst75
--operation mode is normal

inst75 = !A1L67 # !A[9] # !A[10];


--inst78 is inst78
--operation mode is normal

inst78 = A[9] # !A1L67 # !A[10];


--C6L11 is 74244:inst13|36~48
--operation mode is normal

C6L11 = EXINT[5] & (inst78 # INP[5]) # !EXINT[5] & inst75 & (inst78 # INP[5]);


--C6L9 is 74244:inst13|11~48
--operation mode is normal

C6L9 = EXINT[4] & (inst78 # INP[4]) # !EXINT[4] & inst75 & (inst78 # INP[4]);


--C6L7 is 74244:inst13|10~93
--operation mode is normal

C6L7 = EXINT[3] & (inst78 # INP[3]) # !EXINT[3] & inst75 & (inst78 # INP[3]);


--C6L8 is 74244:inst13|10~94
--operation mode is normal

C6L8 = C6L7 & (inst81 # KEY[3]);


--C6L4 is 74244:inst13|6~118
--operation mode is normal

C6L4 = EXINT[2] & (USBINT # inst76) # !EXINT[2] & inst75 & (USBINT # inst76);


--C6L5 is 74244:inst13|6~119
--operation mode is normal

C6L5 = inst78 & (inst81 # KEY[2]) # !inst78 & INP[2] & (inst81 # KEY[2]);


--inst77 is inst77
--operation mode is normal

inst77 = A[10] # A[9] # !A1L69;


--C6L6 is 74244:inst13|6~120
--operation mode is normal

C6L6 = C6L4 & C6L5 & (NMI[1] # inst77);


--C6L1 is 74244:inst13|1~118
--operation mode is normal

C6L1 = EXINT[1] & (8019INT # inst76) # !EXINT[1] & inst75 & (8019INT # inst76);


--C6L2 is 74244:inst13|1~119
--operation mode is normal

C6L2 = inst78 & (inst81 # KEY[1]) # !inst78 & INP[1] & (inst81 # KEY[1]);


--C6L3 is 74244:inst13|1~120
--operation mode is normal

C6L3 = C6L1 & C6L2 & (NMI[0] # inst77);


--A1L65 is inst73~30
--operation mode is normal

A1L65 = !A[10] & !A[9] & A1L63 & !CS1;


--inst42 is inst42
--operation mode is normal

inst42 = !A[11] & !A[12] & !WR & A1L58;


--inst39 is inst39
--operation mode is normal

inst39 = !A[10] & !A[9] & A1L55;


--inst81 is inst81
--operation mode is normal

inst81 = A[10] # !A1L67 # !A[9];


--inst76 is inst76
--operation mode is normal

inst76 = A[10] # !A1L69 # !A[9];