dds32_1.vhd

dds应用主要产生正弦波形

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
library lpm;                -- Altera LPM
use lpm.lpm_components.all;
entity dds32_1 is                              -- DDS主模块          
    generic( freq_width : integer := 32;     -- 输入频率字位宽     
              phase_width : integer := 12;    -- 输入相位字位宽     
              adder_width : integer := 32;    -- 累加器位宽         
              romad_width : integer := 10;    -- 正弦ROM表地址位宽  
              rom_d_width : integer := 10);   -- 正弦ROM表数据位宽  
     port(  clk     : in std_logic;      -- DDS合成时钟  
freqin  : in std_logic_vector (freq_width-1 downto 0);  
                                 -- 频率字输入 
phasein : in std_logic_vector(phase_width-1 downto 0);  
                                 -- 相位字输入    
ddsout  : out std_logic_vector(rom_d_width-1 downto 0));  
                                 -- DDS输出
end entity dds32_1;

architecture behave of dds32_1 is
    signal  acc     : std_logic_vector(adder_width-1 downto 0);
    signal  phaseadd: std_logic_vector(phase_width-1 downto 0);
    signal  romaddr : std_logic_vector(romad_width-1 downto 0);
    signal  freqw   : std_logic_vector(freq_width-1 downto 0);
    signal  phasew  : std_logic_vector(phase_width-1 downto 0);
begin
    process (clk)
    begin
        if(clk'event and clk = '1') then
            freqw <= freqin;    -- 频率字输入同步
            phasew <= phasein;  -- 相位字输入同步
            acc <= acc + freqw; -- 相位累加器
        end if;
    end process;
phaseadd <= acc(adder_width-1 downto adder_width-phase_width) + phasew; 
   romaddr <= phaseadd(phase_width-1 downto phase_width-romad_width);
-- sinrom
    i_rom : lpm_rom     -- LPM_rom调用

GENERIC MAP ( LPM_WIDTH => rom_d_width,
                  LPM_WIDTHAD => romad_width,
         LPM_ADDRESS_CONTROL => "UNREGISTERED",
                  LPM_OUTDATA => "REGISTERED",
                     LPM_FILE => "sin_rom.mif"   )-- 指向rom文件
     PORT MAP ( outclock => clk,address => romaddr,q => ddsout );

end architecture behave;