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📄 insnsa.c

📁 汇编编译器的最新版本的源码.买了自己动手写操作系统这本书的人一定要下
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    {I_COMUNEQSS, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+378, IF_SSE5|IF_AMD|IF_SD},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNLEPD[] = {
    {I_COMUNLEPD, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+252, IF_SSE5|IF_AMD|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNLEPS[] = {
    {I_COMUNLEPS, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+108, IF_SSE5|IF_AMD|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNLESD[] = {
    {I_COMUNLESD, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+540, IF_SSE5|IF_AMD|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNLESS[] = {
    {I_COMUNLESS, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+396, IF_SSE5|IF_AMD|IF_SD},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNLTPD[] = {
    {I_COMUNLTPD, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+243, IF_SSE5|IF_AMD|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNLTPS[] = {
    {I_COMUNLTPS, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+99, IF_SSE5|IF_AMD|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNLTSD[] = {
    {I_COMUNLTSD, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+531, IF_SSE5|IF_AMD|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNLTSS[] = {
    {I_COMUNLTSS, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+387, IF_SSE5|IF_AMD|IF_SD},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNORDPD[] = {
    {I_COMUNORDPD, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+225, IF_SSE5|IF_AMD|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNORDPS[] = {
    {I_COMUNORDPS, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+81, IF_SSE5|IF_AMD|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNORDSD[] = {
    {I_COMUNORDSD, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+513, IF_SSE5|IF_AMD|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_COMUNORDSS[] = {
    {I_COMUNORDSS, 3, {XMMREG,XMMREG,RM_XMM,0,0}, nasm_bytecodes+369, IF_SSE5|IF_AMD|IF_SD},
    ITEMPLATE_END
};

static const struct itemplate instrux_CPUID[] = {
    {I_CPUID, 0, {0,0,0,0,0}, nasm_bytecodes+18613, IF_PENT},
    ITEMPLATE_END
};

static const struct itemplate instrux_CPU_READ[] = {
    {I_CPU_READ, 0, {0,0,0,0,0}, nasm_bytecodes+18617, IF_PENT|IF_CYRIX},
    ITEMPLATE_END
};

static const struct itemplate instrux_CPU_WRITE[] = {
    {I_CPU_WRITE, 0, {0,0,0,0,0}, nasm_bytecodes+18621, IF_PENT|IF_CYRIX},
    ITEMPLATE_END
};

static const struct itemplate instrux_CQO[] = {
    {I_CQO, 0, {0,0,0,0,0}, nasm_bytecodes+18625, IF_X64},
    ITEMPLATE_END
};

static const struct itemplate instrux_CRC32[] = {
    {I_CRC32, 2, {REG32,RM_GPR|BITS8,0,0,0}, nasm_bytecodes+37, IF_SSE42},
    {I_CRC32, 2, {REG32,RM_GPR|BITS16,0,0,0}, nasm_bytecodes+46, IF_SSE42},
    {I_CRC32, 2, {REG32,RM_GPR|BITS32,0,0,0}, nasm_bytecodes+46, IF_SSE42},
    {I_CRC32, 2, {REG64,RM_GPR|BITS8,0,0,0}, nasm_bytecodes+36, IF_SSE42|IF_X64},
    {I_CRC32, 2, {REG64,RM_GPR|BITS64,0,0,0}, nasm_bytecodes+45, IF_SSE42|IF_X64},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTDQ2PD[] = {
    {I_CVTDQ2PD, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15104, IF_WILLAMETTE|IF_SSE2|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTDQ2PS[] = {
    {I_CVTDQ2PS, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15110, IF_WILLAMETTE|IF_SSE2|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTPD2DQ[] = {
    {I_CVTPD2DQ, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15116, IF_WILLAMETTE|IF_SSE2|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTPD2PI[] = {
    {I_CVTPD2PI, 2, {MMXREG,RM_XMM,0,0,0}, nasm_bytecodes+15122, IF_WILLAMETTE|IF_SSE2|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTPD2PS[] = {
    {I_CVTPD2PS, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15128, IF_WILLAMETTE|IF_SSE2|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTPH2PS[] = {
    {I_CVTPH2PS, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+9484, IF_SSE5|IF_AMD|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTPI2PD[] = {
    {I_CVTPI2PD, 2, {XMMREG,RM_MMX,0,0,0}, nasm_bytecodes+15134, IF_WILLAMETTE|IF_SSE2|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTPI2PS[] = {
    {I_CVTPI2PS, 2, {XMMREG,RM_MMX,0,0,0}, nasm_bytecodes+14384, IF_KATMAI|IF_SSE|IF_MMX|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTPS2DQ[] = {
    {I_CVTPS2DQ, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15140, IF_WILLAMETTE|IF_SSE2|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTPS2PD[] = {
    {I_CVTPS2PD, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15146, IF_WILLAMETTE|IF_SSE2|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTPS2PH[] = {
    {I_CVTPS2PH, 2, {RM_XMM,XMMREG,0,0,0}, nasm_bytecodes+9491, IF_SSE5|IF_AMD|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTPS2PI[] = {
    {I_CVTPS2PI, 2, {MMXREG,RM_XMM,0,0,0}, nasm_bytecodes+14390, IF_KATMAI|IF_SSE|IF_MMX|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTSD2SI[] = {
    {I_CVTSD2SI, 2, {REG32,XMMREG,0,0,0}, nasm_bytecodes+8127, IF_WILLAMETTE|IF_SSE2|IF_SQ|IF_AR1},
    {I_CVTSD2SI, 2, {REG32,MEMORY,0,0,0}, nasm_bytecodes+8127, IF_WILLAMETTE|IF_SSE2|IF_SQ|IF_AR1},
    {I_CVTSD2SI, 2, {REG64,XMMREG,0,0,0}, nasm_bytecodes+8126, IF_X64|IF_SSE2|IF_SQ|IF_AR1},
    {I_CVTSD2SI, 2, {REG64,MEMORY,0,0,0}, nasm_bytecodes+8126, IF_X64|IF_SSE2|IF_SQ|IF_AR1},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTSD2SS[] = {
    {I_CVTSD2SS, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15152, IF_WILLAMETTE|IF_SSE2|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTSI2SD[] = {
    {I_CVTSI2SD, 2, {XMMREG,MEMORY,0,0,0}, nasm_bytecodes+8134, IF_WILLAMETTE|IF_SSE2|IF_SD|IF_AR1},
    {I_CVTSI2SD, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, nasm_bytecodes+8134, IF_WILLAMETTE|IF_SSE2|IF_SD|IF_AR1},
    {I_CVTSI2SD, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, nasm_bytecodes+8133, IF_X64|IF_SSE2|IF_SQ|IF_AR1},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTSI2SS[] = {
    {I_CVTSI2SS, 2, {XMMREG,MEMORY,0,0,0}, nasm_bytecodes+7861, IF_KATMAI|IF_SSE|IF_SD|IF_AR1},
    {I_CVTSI2SS, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, nasm_bytecodes+7861, IF_KATMAI|IF_SSE|IF_SD|IF_AR1},
    {I_CVTSI2SS, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, nasm_bytecodes+7860, IF_X64|IF_SSE|IF_SQ|IF_AR1},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTSS2SD[] = {
    {I_CVTSS2SD, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15158, IF_WILLAMETTE|IF_SSE2|IF_SD},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTSS2SI[] = {
    {I_CVTSS2SI, 2, {REG32,XMMREG,0,0,0}, nasm_bytecodes+7868, IF_KATMAI|IF_SSE|IF_SD|IF_AR1},
    {I_CVTSS2SI, 2, {REG32,MEMORY,0,0,0}, nasm_bytecodes+7868, IF_KATMAI|IF_SSE|IF_SD|IF_AR1},
    {I_CVTSS2SI, 2, {REG64,XMMREG,0,0,0}, nasm_bytecodes+7867, IF_X64|IF_SSE|IF_SD|IF_AR1},
    {I_CVTSS2SI, 2, {REG64,MEMORY,0,0,0}, nasm_bytecodes+7867, IF_X64|IF_SSE|IF_SD|IF_AR1},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTTPD2DQ[] = {
    {I_CVTTPD2DQ, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15170, IF_WILLAMETTE|IF_SSE2|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTTPD2PI[] = {
    {I_CVTTPD2PI, 2, {MMXREG,RM_XMM,0,0,0}, nasm_bytecodes+15164, IF_WILLAMETTE|IF_SSE2|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTTPS2DQ[] = {
    {I_CVTTPS2DQ, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15176, IF_WILLAMETTE|IF_SSE2|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTTPS2PI[] = {
    {I_CVTTPS2PI, 2, {MMXREG,RM_XMM,0,0,0}, nasm_bytecodes+14396, IF_KATMAI|IF_SSE|IF_MMX|IF_SQ},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTTSD2SI[] = {
    {I_CVTTSD2SI, 2, {REG32,XMMREG,0,0,0}, nasm_bytecodes+8141, IF_WILLAMETTE|IF_SSE2|IF_SQ|IF_AR1},
    {I_CVTTSD2SI, 2, {REG32,MEMORY,0,0,0}, nasm_bytecodes+8141, IF_WILLAMETTE|IF_SSE2|IF_SQ|IF_AR1},
    {I_CVTTSD2SI, 2, {REG64,XMMREG,0,0,0}, nasm_bytecodes+8140, IF_X64|IF_SSE2|IF_SQ|IF_AR1},
    {I_CVTTSD2SI, 2, {REG64,MEMORY,0,0,0}, nasm_bytecodes+8140, IF_X64|IF_SSE2|IF_SQ|IF_AR1},
    ITEMPLATE_END
};

static const struct itemplate instrux_CVTTSS2SI[] = {
    {I_CVTTSS2SI, 2, {REG32,RM_XMM,0,0,0}, nasm_bytecodes+7875, IF_KATMAI|IF_SSE|IF_SD|IF_AR1},
    {I_CVTTSS2SI, 2, {REG64,RM_XMM,0,0,0}, nasm_bytecodes+7874, IF_X64|IF_SSE|IF_SD|IF_AR1},
    ITEMPLATE_END
};

static const struct itemplate instrux_CWD[] = {
    {I_CWD, 0, {0,0,0,0,0}, nasm_bytecodes+18629, IF_8086},
    ITEMPLATE_END
};

static const struct itemplate instrux_CWDE[] = {
    {I_CWDE, 0, {0,0,0,0,0}, nasm_bytecodes+18633, IF_386},
    ITEMPLATE_END
};

static const struct itemplate instrux_DAA[] = {
    {I_DAA, 0, {0,0,0,0,0}, nasm_bytecodes+19632, IF_8086|IF_NOLONG},
    ITEMPLATE_END
};

static const struct itemplate instrux_DAS[] = {
    {I_DAS, 0, {0,0,0,0,0}, nasm_bytecodes+19635, IF_8086|IF_NOLONG},
    ITEMPLATE_END
};

static const struct itemplate instrux_DB[] = {
    ITEMPLATE_END
};

static const struct itemplate instrux_DD[] = {
    ITEMPLATE_END
};

static const struct itemplate instrux_DEC[] = {
    {I_DEC, 1, {REG16,0,0,0,0}, nasm_bytecodes+18637, IF_8086|IF_NOLONG},
    {I_DEC, 1, {REG32,0,0,0,0}, nasm_bytecodes+18641, IF_386|IF_NOLONG},
    {I_DEC, 1, {RM_GPR|BITS8,0,0,0,0}, nasm_bytecodes+18645, IF_8086},
    {I_DEC, 1, {RM_GPR|BITS16,0,0,0,0}, nasm_bytecodes+16958, IF_8086},
    {I_DEC, 1, {RM_GPR|BITS32,0,0,0,0}, nasm_bytecodes+16963, IF_386},
    {I_DEC, 1, {RM_GPR|BITS64,0,0,0,0}, nasm_bytecodes+16968, IF_X64},
    ITEMPLATE_END
};

static const struct itemplate instrux_DIV[] = {
    {I_DIV, 1, {RM_GPR|BITS8,0,0,0,0}, nasm_bytecodes+18649, IF_8086},
    {I_DIV, 1, {RM_GPR|BITS16,0,0,0,0}, nasm_bytecodes+16973, IF_8086},
    {I_DIV, 1, {RM_GPR|BITS32,0,0,0,0}, nasm_bytecodes+16978, IF_386},
    {I_DIV, 1, {RM_GPR|BITS64,0,0,0,0}, nasm_bytecodes+16983, IF_X64},
    ITEMPLATE_END
};

static const struct itemplate instrux_DIVPD[] = {
    {I_DIVPD, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15182, IF_WILLAMETTE|IF_SSE2|IF_SO},
    ITEMPLATE_END
};

static const struct itemplate instrux_DIVPS[] = {
    {I_DIVPS, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+14402, IF_KATMAI|IF_SSE},
    ITEMPLATE_END
};

static const struct itemplate instrux_DIVSD[] = {
    {I_DIVSD, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+15188, IF_WILLAMETTE|IF_SSE2},
    ITEMPLATE_END
};

static const struct itemplate instrux_DIVSS[] = {
    {I_DIVSS, 2, {XMMREG,RM_XMM,0,0,0}, nasm_bytecodes+14408, IF_KATMAI|IF_SSE},
    ITEMPLATE_END
};

static const struct itemplate instrux_DMINT[] = {
    {I_DMINT, 0, {0,0,0,0,0}, nasm_bytecodes+18653, IF_P6|IF_CYRIX},
    ITEMPLATE_END
};

static const struct itemplate instrux_DO[] = {
    ITEMPLATE_END
};

static const struct itemplate instrux_DPPD[] = {
    {I_DPPD, 3, {XMMREG,RM_XMM,IMMEDIATE,0,0}, nasm_bytecodes+6144, IF_SSE41},
    ITEMPLATE_END
};

static const struct itemplate instrux_DPPS[] = {
    {I_DPPS, 3, {XMMREG,RM_XMM,IMMEDIATE,0,0}, nasm_bytecodes+6152, IF_SSE41},
    ITEMPLATE_END
};

static const struct itemplate instrux_DQ[] = {
    ITEMPLATE_END
};

static const struct itemplate instrux_DT[] = {
    ITEMPLATE_END
};

static const struct itemplate instrux_DW[] = {
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