📄 2413addr.h
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#define rWTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data
#define rWTCNT (*(volatile unsigned *)0x53000008) //Watch-dog timer count
//chapter18 MMC/SD/SDI CONTROLLER
//chapter18 MMC/SD/SDI CONTROLLER
#define rSDICON (*(volatile unsigned *)0x5A000000) //SDI Control
#define rSDIPRE (*(volatile unsigned *)0x5A000004) //SDI baud rate prescaler
#define rSDICmdARG (*(volatile unsigned *)0x5A000008) //SDI command argument
#define rSDICmdCON (*(volatile unsigned *)0x5A00000c) //SDI command control
#define rSDICmdSTA (*(volatile unsigned *)0x5A000010) //SDI command status
#define rSDIRSP0 (*(volatile unsigned *)0x5A000014) //SDI response 0
#define rSDIRSP1 (*(volatile unsigned *)0x5A000018) //SDI response 1
#define rSDIRSP2 (*(volatile unsigned *)0x5A00001c) //SDI response 2
#define rSDIRSP3 (*(volatile unsigned *)0x5A000020) //SDI response 3
#define rSDIDTIMER (*(volatile unsigned *)0x5A000024) //SDI data/busy timer
#define rSDIBSIZE (*(volatile unsigned *)0x5A000028) //SDI block size
#define rSDIDCON (*(volatile unsigned *)0x5A00002c) //SDI data control
#define rSDIDCNT (*(volatile unsigned *)0x5A000030) //SDI data remain counter
#define rSDIDSTA (*(volatile unsigned *)0x5A000034) //SDI data status
#define rSDIFSTA (*(volatile unsigned *)0x5A000038) //SDI FIFO status
#define rSDIINTMSK (*(volatile unsigned *)0x5A00003c) //SDI Interrupt Mask
#ifdef __BIG_ENDIAN /* edited for 2413 */
#define rSDIDAT (*(volatile unsigned *)0x5A00004c) //SDI data
#define SDIDAT 0x5A00004c
#else // Little Endian
#define rSDIDAT (*(volatile unsigned *)0x5A000040) //SDI data
#define SDIDAT 0x5A000040
#endif //SD Interface
//chapter19 IIC
#define rIICCON (*(volatile unsigned *)0x54000000) //IIC control
#define rIICSTAT (*(volatile unsigned *)0x54000004) //IIC control/status
#define rIICADD (*(volatile unsigned *)0x54000008) //IIC address
#define rIICDS (*(volatile unsigned *)0x5400000c) //IIC transmit/receive data shift
#define rIICLC (*(volatile unsigned *)0x54000010) //IIC line control register
//chapter20 IIS
#define rIISCON (*(volatile unsigned *)0x55000000) //IIS Control
#define rIISMOD (*(volatile unsigned *)0x55000004) //IIS Mode
#define rIISFIC (*(volatile unsigned *)0x55000008) //IIS FIFO control
#define rIISPSR (*(volatile unsigned *)0x5500000c) //IIS clock divider control
#define rIISTXD (*(volatile unsigned *)0x55000010) //IIS tracsmit data
#define rIISRXD (*(volatile unsigned *)0x55000014) //IIS recelve data
//chapter21 SPI
#define rSPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
#define rSPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status
#define rSPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
#define rSPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud rate prescaler
#define rSPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data
#define rSPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data
#define rSPTXFIFO0 (*(volatile unsigned *)0x59000018) //SPI0 Tx FIFO
#define rSPRXFIFO0 (*(volatile unsigned *)0x5900001C) //SPI0 Rx FIFO
#define rSPRDATB0 (*(volatile unsigned *)0x59000020) //SPI0 Rx Data
#define rSPFIC0 (*(volatile unsigned *)0x59000024) //SPI0 Rx FIFO Interrupt and DMA control
#define rSPCON1 (*(volatile unsigned *)0x59000100) //SPI1 control
#define rSPSTA1 (*(volatile unsigned *)0x59000104) //SPI1 status
#define rSPPIN1 (*(volatile unsigned *)0x59000108) //SPI1 pin control
#define rSPPRE1 (*(volatile unsigned *)0x5900010c) //SPI1 baud rate prescaler
#define rSPTDAT1 (*(volatile unsigned *)0x59000110) //SPI1 Tx data
#define rSPRDAT1 (*(volatile unsigned *)0x59000114) //SPI1 Rx data
#define rSPTXFIFO1 (*(volatile unsigned *)0x59000118) //SPI1 Tx FIFO
#define rSPRXFIFO1 (*(volatile unsigned *)0x5900011C) //SPI1 Rx FIFO
#define rSPRDATB1 (*(volatile unsigned *)0x59000120) //SPI1 Rx Data
#define rSPFIC1 (*(volatile unsigned *)0x59000124) //SPI1 Rx FIFO Interrupt and DMA control
//chapter22 Camera Interface
#define rCISRCFMT (*(volatile unsigned *)0x4D800000) //Input Source Format
#define rCIWDOFST (*(volatile unsigned *)0x4D800004) //Window offset
#define rCIGCTRL (*(volatile unsigned *)0x4D800008) //Global control
#define rCIFCTRL1 (*(volatile unsigned *)0x4D80000C) //flash control 1
#define rCIFCTRL2 (*(volatile unsigned *)0x4D800010) //flash control 2
#define rCIDOWSFT2 (*(volatile unsigned *)0x4D800014) //Window option 2
#define rCICOYSA1 (*(volatile unsigned *)0x4D800018) //Y1 frame start address for codec DMA
#define rCICOYSA2 (*(volatile unsigned *)0x4D80001C) //Y2 frame start address for codec DMA
#define rCICOYSA3 (*(volatile unsigned *)0x4D800020) //Y3 frame start address for codec DMA
#define rCICOYSA4 (*(volatile unsigned *)0x4D800024) //Y4 frame start address for codec DMA
#define rCICOCBSA1 (*(volatile unsigned *)0x4D800028) //Cb1 frame start address for codec DMA
#define rCICOCBSA2 (*(volatile unsigned *)0x4D80002C) //Cb2 frame start address for codec DMA
#define rCICOCBSA3 (*(volatile unsigned *)0x4D800030) //Cb3 frame start address for codec DMA
#define rCICOCBSA4 (*(volatile unsigned *)0x4D800034) //Cb4 frame start address for codec DMA
#define rCICOCRSA1 (*(volatile unsigned *)0x4D800038) //Cr1 frame start address for codec DMA
#define rCICOCRSA2 (*(volatile unsigned *)0x4D80003C) //Cr2 frame start address for codec DMA
#define rCICOCRSA3 (*(volatile unsigned *)0x4D800040) //Cr3 frame start address for codec DMA
#define rCICOCRSA4 (*(volatile unsigned *)0x4D800044) //Cr4 frame start address for codec DMA
#define rCICOTRGFMT (*(volatile unsigned *)0x4D800048) //Target image format of codex DMA
#define rCICOCTRL (*(volatile unsigned *)0x4D80004C) //Codec DMA comtrol
#define rCICOSCPRERATIO (*(volatile unsigned *)0x4D800050) //Codec pre-scaler ratio control
#define rCICOSCPREDST (*(volatile unsigned *)0x4D800054) //Codec pre-scaler desitination format
#define rCICOSCCTRL (*(volatile unsigned *)0x4D800058) //Codec main-scaler control
#define rCICOTAREA (*(volatile unsigned *)0x4D80005C) //Codec pre-scaler desination format
#define rCICOSTATUS (*(volatile unsigned *)0x4D800064) //Codec path status
#define rCIIMGCPT (*(volatile unsigned *)0x4D8000A0) //Imahe capture enable command
#define rCICOCPTSEQ (*(volatile unsigned *)0x4D8000A4) //Codec dma capture sequence related
#define rCICOSCOS (*(volatile unsigned *)0x4D8000A8) //Codec scan line offset related
#define rCIIMGEFF (*(volatile unsigned *)0x4D8000B0) //Imahe Effects related
//Exception vector
#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xc))
#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1c))
// Interrupt vector
#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2c))
#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
#define pISR_CAM (*(unsigned *)(_ISR_STARTADDRESS+0x38)) // Added for 2442.
#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3c))
#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) //Changed to pISR_WDT_AC97 for 2442A
#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4c))
#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5c))
#define pISR_LCD (*(unsigned *)(_ISR_STARTADDRESS+0x60))
#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6c))
#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7c))
#define pISR_NFCON (*(unsigned *)(_ISR_STARTADDRESS+0x80)) // Added for 2442.
#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8c))
#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0x9c))
// PENDING BIT
#define BIT_EINT0 (0x1)
#define BIT_EINT1 (0x1<<1)
#define BIT_EINT2 (0x1<<2)
#define BIT_EINT3 (0x1<<3)
#define BIT_EINT4_7 (0x1<<4)
#define BIT_EINT8_23 (0x1<<5)
#define BIT_CAM (0x1<<6)
#define BIT_BAT_FLT (0x1<<7)
#define BIT_TICK (0x1<<8)
#define BIT_WDT (0x1<<9)
#define BIT_TIMER0 (0x1<<10)
#define BIT_TIMER1 (0x1<<11)
#define BIT_TIMER2 (0x1<<12)
#define BIT_TIMER3 (0x1<<13)
#define BIT_TIMER4 (0x1<<14)
#define BIT_UART2 (0x1<<15)
#define BIT_LCD (0x1<<16)
#define BIT_DMA0 (0x1<<17)
#define BIT_DMA1 (0x1<<18)
#define BIT_DMA2 (0x1<<19)
#define BIT_DMA3 (0x1<<20)
#define BIT_SDI (0x1<<21)
#define BIT_SPI0 (0x1<<22)
#define BIT_UART1 (0x1<<23)
#define BIT_NFCON (0x1<<24)
#define BIT_USBD (0x1<<25)
#define BIT_USBH (0x1<<26)
#define BIT_IIC (0x1<<27)
#define BIT_UART0 (0x1<<28)
#define BIT_SPI1 (0x1<<29)
#define BIT_RTC (0x1<<30)
#define BIT_ADC (0x1<<31)
#define BIT_ALLMSK (0xffffffff)
#define BIT_SUB_ALLMSK (0x7fff) //Changed from 0x7ff to 0x7fff for 2442A
#define BIT_SUB_CF (0x1<<14)
#define BIT_SUB_SDI (0x1<<13)
#define BIT_SUB_ADC (0x1<<10)
#define BIT_SUB_TC (0x1<<9)
#define BIT_SUB_ERR2 (0x1<<8)
#define BIT_SUB_TXD2 (0x1<<7)
#define BIT_SUB_RXD2 (0x1<<6)
#define BIT_SUB_ERR1 (0x1<<5)
#define BIT_SUB_TXD1 (0x1<<4)
#define BIT_SUB_RXD1 (0x1<<3)
#define BIT_SUB_ERR0 (0x1<<2)
#define BIT_SUB_TXD0 (0x1<<1)
#define BIT_SUB_RXD0 (0x1<<0)
#define ClearPending(bit) {\
rSRCPND = bit;\
rINTPND = bit;\
rINTPND;\
}
//Wait until rINTPND is changed for the case that the ISR is very short.
// The effect of reading "rINTPND;" : Waiting until rINTPND is changed.
// When you access any address, write buffer must be cleared if you want to read this address.
// Otherwise, twice interrupt request could be occured per one interrupt.
// in the case that the ISR is very short.
#ifdef __cplusplus
}
#endif
#endif
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