defbf561.h

此代码实现blackfin系列DSP的上电监控代码

						// Loop Count
#define DMA2_11_CURR_Y_COUNT	0xFFC00EF8	// DMA2 Channel 11 Current Outer
						// Loop Count
#define DMA2_11_IRQ_STATUS	0xFFC00EE8	// DMA2 Channel 11 Interrupt
						// /Status Register
#define DMA2_11_PERIPHERAL_MAP	0xFFC00EEC	// DMA2 Channel 11 Peripheral 
						// Map Register

// Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF)
#define MDMA2_D0_CONFIG		0xFFC00F08	// MemDMA2 Stream 0 Destination
						// Configuration register
#define MDMA2_D0_NEXT_DESC_PTR	0xFFC00F00	// MemDMA2 Stream 0
						// Destination Next
						// Descriptor Ptr Reg
#define MDMA2_D0_START_ADDR	0xFFC00F04	// MemDMA2 Stream 0 Destination
						// Start Address
#define MDMA2_D0_X_COUNT	0xFFC00F10	// MemDMA2 Stream 0 Dest
						// Inner-Loop Count register
#define MDMA2_D0_Y_COUNT	0xFFC00F18	// MemDMA2 Stream 0 Dest
						// Outer-Loop Count register
#define MDMA2_D0_X_MODIFY	0xFFC00F14	// MemDMA2 Stream 0 Dest
						// Inner-Loop Address-Increment
#define MDMA2_D0_Y_MODIFY	0xFFC00F1C	// MemDMA2 Stream 0 Dest
						// Outer-Loop Address-Increment
#define MDMA2_D0_CURR_DESC_PTR	0xFFC00F20	// MemDMA2 Stream 0 Dest
						// Current Descriptor Ptr reg
#define MDMA2_D0_CURR_ADDR	0xFFC00F24	// MemDMA2 Stream 0 Destination
						// Current Address
#define MDMA2_D0_CURR_X_COUNT	0xFFC00F30	// MemDMA2 Stream 0 Dest
						// Current Inner-Loop Count reg
#define MDMA2_D0_CURR_Y_COUNT	0xFFC00F38	// MemDMA2 Stream 0 Dest
						// Current Outer-Loop Count reg
#define MDMA2_D0_IRQ_STATUS	0xFFC00F28	// MemDMA2 Stream 0 Dest
						// Interrupt/Status Register
#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C	// MemDMA2 Stream 0
						// Destination Peripheral Map 
						// register

#define MDMA2_S0_CONFIG		0xFFC00F48	// MemDMA2 Stream 0 Source
						// Configuration register
#define MDMA2_S0_NEXT_DESC_PTR	0xFFC00F40	// MemDMA2 Stream 0 Source
						// Next Descriptor Ptr Reg
#define MDMA2_S0_START_ADDR	0xFFC00F44	// MemDMA2 Stream 0 Source
						// Start Address
#define MDMA2_S0_X_COUNT	0xFFC00F50	// MemDMA2 Stream 0 Source
						// Inner-Loop Count register
#define MDMA2_S0_Y_COUNT	0xFFC00F58	// MemDMA2 Stream 0 Source
						// Outer-Loop Count register
#define MDMA2_S0_X_MODIFY	0xFFC00F54	// MemDMA2 Stream 0 Src
						// Inner-Loop Addr-Increment reg
#define MDMA2_S0_Y_MODIFY	0xFFC00F5C	// MemDMA2 Stream 0 Src
						// Outer-Loop Addr-Increment reg
#define MDMA2_S0_CURR_DESC_PTR	0xFFC00F60	// MemDMA2 Stream 0 Source
						// Current Descriptor Ptr reg
#define MDMA2_S0_CURR_ADDR	0xFFC00F64	// MemDMA2 Stream 0 Source
						// Current Address
#define MDMA2_S0_CURR_X_COUNT	0xFFC00F70	// MemDMA2 Stream 0 Src
						// Current Inner-Loop Count reg
#define MDMA2_S0_CURR_Y_COUNT	0xFFC00F78	// MemDMA2 Stream 0 Src
						// Current Outer-Loop Count reg
#define MDMA2_S0_IRQ_STATUS	0xFFC00F68	// MemDMA2 Stream 0 Source
						// Interrupt/Status Register
#define MDMA2_S0_PERIPHERAL_MAP	0xFFC00F6C	// MemDMA2 Stream 0 Source
						// Peripheral Map register

#define MDMA2_D1_CONFIG		0xFFC00F88	// MemDMA2 Stream 1 Destination
						// Configuration register
#define MDMA2_D1_NEXT_DESC_PTR	0xFFC00F80	// MemDMA2 Stream 1
						// Destination Next
						// Descriptor Ptr Reg
#define MDMA2_D1_START_ADDR	0xFFC00F84	// MemDMA2 Stream 1 Destination
						// Start Address
#define MDMA2_D1_X_COUNT	0xFFC00F90	// MemDMA2 Stream 1 Dest
						// Inner-Loop Count register
#define MDMA2_D1_Y_COUNT	0xFFC00F98	// MemDMA2 Stream 1 Dest
						// Outer-Loop Count register
#define MDMA2_D1_X_MODIFY	0xFFC00F94	// MemDMA2 Stream 1 Dest
						// Inner-Loop Address-Increment
#define MDMA2_D1_Y_MODIFY	0xFFC00F9C	// MemDMA2 Stream 1 Dest
						// Outer-Loop Address-Increment
#define MDMA2_D1_CURR_DESC_PTR	0xFFC00FA0	// MemDMA2 Stream 1
						// Destination Current
						// Descriptor Ptr
#define MDMA2_D1_CURR_ADDR	0xFFC00FA4	// MemDMA2 Stream 1 Destination
						// Current Address reg
#define MDMA2_D1_CURR_X_COUNT	0xFFC00FB0	// MemDMA2 Stream 1 Dest
						// Current Inner-Loop Count reg
#define MDMA2_D1_CURR_Y_COUNT	0xFFC00FB8	// MemDMA2 Stream 1 Dest
						// Current Outer-Loop Count reg
#define MDMA2_D1_IRQ_STATUS	0xFFC00FA8	// MemDMA2 Stream 1 Destination
						// Interrupt/Status Reg
#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC	// MemDMA2 Stream 1
						// Destination Peripheral Map 
						// register

#define MDMA2_S1_CONFIG		0xFFC00FC8	// MemDMA2 Stream 1 Source
						// Configuration register
#define MDMA2_S1_NEXT_DESC_PTR	0xFFC00FC0	// MemDMA2 Stream 1 Source
						// Next Descriptor Ptr Reg
#define MDMA2_S1_START_ADDR	0xFFC00FC4	// MemDMA2 Stream 1 Source
						// Start Address
#define MDMA2_S1_X_COUNT	0xFFC00FD0	// MemDMA2 Stream 1 Source
						// Inner-Loop Count register
#define MDMA2_S1_Y_COUNT	0xFFC00FD8	// MemDMA2 Stream 1 Source
						// Outer-Loop Count register
#define MDMA2_S1_X_MODIFY	0xFFC00FD4	// MemDMA2 Stream 1 Src
						// Inner-Loop Address-Increment
#define MDMA2_S1_Y_MODIFY	0xFFC00FDC	// MemDMA2 Stream 1 Source
						// Outer-Loop Address-Increment
#define MDMA2_S1_CURR_DESC_PTR	0xFFC00FE0	// MemDMA2 Stream 1 Source
						// Current Descriptor Ptr reg
#define MDMA2_S1_CURR_ADDR	0xFFC00FE4	// MemDMA2 Stream 1 Source
						// Current Address
#define MDMA2_S1_CURR_X_COUNT	0xFFC00FF0	// MemDMA2 Stream 1 Source
						// Current Inner-Loop Count
#define MDMA2_S1_CURR_Y_COUNT	0xFFC00FF8	// MemDMA2 Stream 1 Source
						// Current Outer-Loop Count
#define MDMA2_S1_IRQ_STATUS	0xFFC00FE8	// MemDMA2 Stream 1 Source
						// Interrupt/Status Register
#define MDMA2_S1_PERIPHERAL_MAP	0xFFC00FEC	// MemDMA2 Stream 1 Source
						// Peripheral Map register

// Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF)
#define IMDMA_D0_CONFIG		0xFFC01808	// IMDMA Stream 0 Destination
						// Configuration
#define IMDMA_D0_NEXT_DESC_PTR	0xFFC01800	// IMDMA Stream 0 Destination 
						// Next Descriptor Ptr Reg
#define IMDMA_D0_START_ADDR	0xFFC01804	// IMDMA Stream 0 Destination
						// Start Address
#define IMDMA_D0_X_COUNT	0xFFC01810	// IMDMA Stream 0 Destination
						// Inner-Loop Count
#define IMDMA_D0_Y_COUNT	0xFFC01818	// IMDMA Stream 0 Destination
						// Outer-Loop Count
#define IMDMA_D0_X_MODIFY	0xFFC01814	// IMDMA Stream 0 Dest
						// Inner-Loop Address-Increment
#define IMDMA_D0_Y_MODIFY	0xFFC0181C	// IMDMA Stream 0 Dest
						// Outer-Loop Address-Increment
#define IMDMA_D0_CURR_DESC_PTR	0xFFC01820	// IMDMA Stream 0 Destination 
						// Current Descriptor Ptr
#define IMDMA_D0_CURR_ADDR	0xFFC01824	// IMDMA Stream 0 Destination
						// Current Address
#define IMDMA_D0_CURR_X_COUNT	0xFFC01830	// IMDMA Stream 0 Destination 
						// Current Inner-Loop Count
#define IMDMA_D0_CURR_Y_COUNT	0xFFC01838	// IMDMA Stream 0 Destination 
						// Current Outer-Loop Count
#define IMDMA_D0_IRQ_STATUS	0xFFC01828	// IMDMA Stream 0 Destination
						// Interrupt/Status

#define IMDMA_S0_CONFIG		0xFFC01848	// IMDMA Stream 0 Source
						// Configuration
#define IMDMA_S0_NEXT_DESC_PTR	0xFFC01840	// IMDMA Stream 0 Source Next 
						// Descriptor Ptr Reg
#define IMDMA_S0_START_ADDR	0xFFC01844	// IMDMA Stream 0 Source Start
						// Address
#define IMDMA_S0_X_COUNT	0xFFC01850	// IMDMA Stream 0 Source
						// Inner-Loop Count
#define IMDMA_S0_Y_COUNT	0xFFC01858	// IMDMA Stream 0 Source
						// Outer-Loop Count
#define IMDMA_S0_X_MODIFY	0xFFC01854	// IMDMA Stream 0 Source
						// Inner-Loop Address-Increment
#define IMDMA_S0_Y_MODIFY	0xFFC0185C	// IMDMA Stream 0 Source
						// Outer-Loop Address-Increment
#define IMDMA_S0_CURR_DESC_PTR	0xFFC01860	// IMDMA Stream 0 Source
						// Current Descriptor Ptr reg
#define IMDMA_S0_CURR_ADDR	0xFFC01864	// IMDMA Stream 0 Source Current
						// Address
#define IMDMA_S0_CURR_X_COUNT	0xFFC01870	// IMDMA Stream 0 Source
						// Current Inner-Loop Count
#define IMDMA_S0_CURR_Y_COUNT	0xFFC01878	// IMDMA Stream 0 Source
						// Current Outer-Loop Count
#define IMDMA_S0_IRQ_STATUS	0xFFC01868	// IMDMA Stream 0 Source
						// Interrupt/Status

#define IMDMA_D1_CONFIG		0xFFC01888	// IMDMA Stream 1 Destination
						// Configuration
#define IMDMA_D1_NEXT_DESC_PTR	0xFFC01880	// IMDMA Stream 1 Destination 
						// Next Descriptor Ptr Reg
#define IMDMA_D1_START_ADDR	0xFFC01884	// IMDMA Stream 1 Destination
						// Start Address
#define IMDMA_D1_X_COUNT	0xFFC01890	// IMDMA Stream 1 Destination
						// Inner-Loop Count
#define IMDMA_D1_Y_COUNT	0xFFC01898	// IMDMA Stream 1 Destination
						// Outer-Loop Count
#define IMDMA_D1_X_MODIFY	0xFFC01894	// IMDMA Stream 1 Dest
						// Inner-Loop Address-Increment
#define IMDMA_D1_Y_MODIFY	0xFFC0189C	// IMDMA Stream 1 Dest
						// Outer-Loop Address-Increment
#define IMDMA_D1_CURR_DESC_PTR	0xFFC018A0	// IMDMA Stream 1 Destination 
						// Current Descriptor Ptr
#define IMDMA_D1_CURR_ADDR	0xFFC018A4	// IMDMA Stream 1 Destination
						// Current Address
#define IMDMA_D1_CURR_X_COUNT	0xFFC018B0	// IMDMA Stream 1 Destination 
						// Current Inner-Loop Count
#define IMDMA_D1_CURR_Y_COUNT	0xFFC018B8	// IMDMA Stream 1 Destination 
						// Current Outer-Loop Count
#define IMDMA_D1_IRQ_STATUS	0xFFC018A8	// IMDMA Stream 1 Destination
						// Interrupt/Status

#define IMDMA_S1_CONFIG		0xFFC018C8	// IMDMA Stream 1 Source
						// Configuration
#define IMDMA_S1_NEXT_DESC_PTR	0xFFC018C0	// IMDMA Stream 1 Source Next 
						// Descriptor Ptr Reg
#define IMDMA_S1_START_ADDR	0xFFC018C4	// IMDMA Stream 1 Source Start
						// Address
#define IMDMA_S1_X_COUNT	0xFFC018D0	// IMDMA Stream 1 Source
						// Inner-Loop Count
#define IMDMA_S1_Y_COUNT	0xFFC018D8	// IMDMA Stream 1 Source
						// Outer-Loop Count
#define IMDMA_S1_X_MODIFY	0xFFC018D4	// IMDMA Stream 1 Source
						// Inner-Loop Address-Increment
#define IMDMA_S1_Y_MODIFY	0xFFC018DC	// IMDMA Stream 1 Source
						// Outer-Loop Address-Increment
#define IMDMA_S1_CURR_DESC_PTR	0xFFC018E0	// IMDMA Stream 1 Source
						// Current Descriptor Ptr reg
#define IMDMA_S1_CURR_ADDR	0xFFC018E4	// IMDMA Stream 1 Source Current
						// Address
#define IMDMA_S1_CURR_X_COUNT	0xFFC018F0	// IMDMA Stream 1 Source
						// Current Inner-Loop Count
#define IMDMA_S1_CURR_Y_COUNT	0xFFC018F8	// IMDMA Stream 1 Source
						// Current Outer-Loop Count
#define IMDMA_S1_IRQ_STATUS	0xFFC018E8	// IMDMA Stream 1 Source
						// Interrupt/Status

//****************************************************************************
// System MMR Register Bits
//****************************************************************************

// ********************* PLL AND RESET MASKS ************************

//// PLL_CTL Masks
#define PLL_CLKIN              0x00000000	// Pass CLKIN to PLL
#define PLL_CLKIN_DIV2         0x00000001	// Pass CLKIN/2 to PLL
#define PLL_OFF                0x00000002	// Shut off PLL clocks
#define STOPCK_OFF             0x00000008	// Core clock off
#define PDWN                   0x00000020	// Put the PLL in a Deep
						// Sleep state
#define BYPASS                 0x00000100	// Bypass the PLL

//// PLL_DIV Masks

#define SCLK_DIV(x)  (x)	// SCLK = VCO / x

#define CCLK_DIV1              0x00000000	// CCLK = VCO / 1
#define CCLK_DIV2              0x00000010	// CCLK = VCO / 2
#define CCLK_DIV4              0x00000020	// CCLK = VCO / 4
#define CCLK_DIV8              0x00000030	// CCLK = VCO / 8

// SWRST Mask
#define SYSTEM_RESET           0x00000007	// Initiates a system
						// software reset
#define SWRST_DBL_FAULT_B      0x00000800	// SWRST Core B Double Fault
#define SWRST_DBL_FAULT_A      0x00001000	// SWRST Core A Double Fault
#define SWRST_WDT_B	       0x00002000	// SWRST Watchdog B
#define SWRST_WDT_A	       0x00004000	// SWRST Watchdog A
#define SWRST_OCCURRED         0x00008000	// SWRST Status

// *************  SYSTEM INTERRUPT CONTROLLER MASKS *****************

// SICu_IARv Masks      
// u = A or B
// v = 0 to 7
// w = 0 or 1

// Per_number = 0 to 63
// IVG_number = 7 to 15  
// Peripheral #Per_number assigned IVG #IVG_number
// Usage: 
//	r0.l = lo(Peripheral_IVG(62, 10));
//	r0.h = hi(Peripheral_IVG(62, 10));
#define Peripheral_IVG(Per_number, IVG_number)    \
				( (IVG_number) -7) << ( ((Per_number)%8) *4)

// SICx_IMASKw Masks
// masks are 32 bit wide, so two writes reguired for "64 bit" wide registers 
#define SIC_UNMASK_ALL         0x00000000	// Unmask all peripheral
						// interrupts
#define SIC_MASK_ALL           0xFFFFFFFF	// Mask all peripheral
						// interrupts
#define SIC_MASK(x)	       (1 << (x))	// Mask Peripheral #x
						// interrupt
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x)))	// Unmask Peripheral #x
						// interrupt

// SIC_IWR Masks
#define IWR_DISABLE_ALL		0x00000000	// Wakeup Disable all
						// peripherals
#define IWR_ENABLE_ALL		0xFFFFFFFF	// Wakeup Enable all
						// peripherals
// x = pos 0 to 31, for 32-63 use value-32
#define IWR_ENABLE(x)		(1 << (x))	// Wakeup Enable Peripheral
						// #x
// Wakeup Disable Peripheral