defbf535.h

此代码实现blackfin系列DSP的上电监控代码

#define IWR_ENABLE13		0x00002000	/* Wakeup Enable Peripheral #13 */
#define IWR_ENABLE14		0x00004000	/* Wakeup Enable Peripheral #14 */
#define IWR_ENABLE15		0x00008000	/* Wakeup Enable Peripheral #15 */
#define IWR_ENABLE16		0x00010000	/* Wakeup Enable Peripheral #16 */
#define IWR_ENABLE17		0x00020000	/* Wakeup Enable Peripheral #17 */
#define IWR_ENABLE18		0x00040000	/* Wakeup Enable Peripheral #18 */
#define IWR_ENABLE19		0x00080000	/* Wakeup Enable Peripheral #19 */
#define IWR_ENABLE20		0x00100000	/* Wakeup Enable Peripheral #20 */
#define IWR_DISABLE0		0xFFFFFFFE	/* Wakeup Disable Peripheral #0 */
#define IWR_DISABLE1		0xFFFFFFFD	/* Wakeup Disable Peripheral #1 */
#define IWR_DISABLE2		0xFFFFFFFB	/* Wakeup Disable Peripheral #2 */
#define IWR_DISABLE3		0xFFFFFFF7	/* Wakeup Disable Peripheral #3 */
#define IWR_DISABLE4		0xFFFFFFEF	/* Wakeup Disable Peripheral #4 */
#define IWR_DISABLE5		0xFFFFFFDF	/* Wakeup Disable Peripheral #5 */
#define IWR_DISABLE6		0xFFFFFFBF	/* Wakeup Disable Peripheral #6 */
#define IWR_DISABLE7		0xFFFFFF7F	/* Wakeup Disable Peripheral #7 */
#define IWR_DISABLE8		0xFFFFFEFF	/* Wakeup Disable Peripheral #8 */
#define IWR_DISABLE9		0xFFFFFDFF	/* Wakeup Disable Peripheral #9 */
#define IWR_DISABLE10		0xFFFFFBFF	/* Wakeup Disable Peripheral #10 */
#define IWR_DISABLE11		0xFFFFF7FF	/* Wakeup Disable Peripheral #11 */
#define IWR_DISABLE12		0xFFFFEFFF	/* Wakeup Disable Peripheral #12 */
#define IWR_DISABLE13		0xFFFFDFFF	/* Wakeup Disable Peripheral #13 */
#define IWR_DISABLE14		0xFFFFBFFF	/* Wakeup Disable Peripheral #14 */
#define IWR_DISABLE15		0xFFFF7FFF	/* Wakeup Disable Peripheral #15 */
#define IWR_DISABLE16		0xFFFEFFFF	/* Wakeup Disable Peripheral #16 */
#define IWR_DISABLE17		0xFFFDFFFF	/* Wakeup Disable Peripheral #17 */
#define IWR_DISABLE18		0xFFFBFFFF	/* Wakeup Disable Peripheral #18 */
#define IWR_DISABLE19		0xFFF7FFFF	/* Wakeup Disable Peripheral #19 */
#define IWR_DISABLE20		0xFFEFFFFF	/* Wakeup Disable Peripheral #20 */

/* WDOGCTL Masks */
#define ENABLE_RESET		0x00000000	/* Set Watchdog Timer to generate reset */
#define ENABLE_NMI		0x00000002	/* Set Watchdog Timer to generate non-maskable interrupt */
#define ENABLE_GPI		0x00000004	/* Set Watchdog Timer to generate general-purpose interrupt */
#define DISABLE_EVT		0x00000006	/* Disable Watchdog Timer interrupts */

/* RTCFAST Mask */
#define ENABLE_PRESCALE		0x00000001	/* Enable prescaler so RTC runs at 1 Hz, Must be set after power-up for proper operation of RTC */

/* SPICTLx Masks */
#define TIMOD			0x00000003	/* Transfer initiation mode and interrupt generation */
#define SZ			0x00000004	/* Send Zero (=0) or last (=1) word when TDBR empty */
#define GM			0x00000008	/* When RDBR full, get more (=1) data or discard (=0) incoming Data */
#define PSSE			0x00000010	/* Enable (=1) Slave-Select input for Master */
#define EMISO			0x00000020	/* Enable (=1) MISO pin as an output. */
#define SIZE			0x00000100	/* Word length (0 => 8 bits, 1 => 16 bits) */
#define LSBF			0x00000200	/* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
#define CPHA			0x00000400	/* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer */
#define CPOL			0x00000800	/* Clock polarity (0 => active-high, 1 => active-low) */
#define MSTR			0x00001000	/* Configures SPI as master (=1) or slave (=0) */
#define WOM			0x00002000	/* Open drain (=1) data output enable (for MOSI and MISO) */
#define SPE			0x00004000	/* SPI module enable (=1), disable (=0) */

/* SPIFLGx Masks */
#define FLS1			0x00000002	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLS2			0x00000004	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLS3			0x00000008	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLS4			0x00000010	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLS5			0x00000020	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLS6			0x00000040	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLS7			0x00000080	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
#define FLG1			0x00000200	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLG2			0x00000400	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLG3			0x00000800	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ 
#define FLG4			0x00001000	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ 
#define FLG5			0x00002000	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ 
#define FLG6			0x00004000	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ 
#define FLG7			0x00008000	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */

/* SPIFLGx Bit Positions */
#define FLS1_P			0x00000001	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLS2_P			0x00000002	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLS3_P			0x00000003	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLS4_P			0x00000004	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLS5_P			0x00000005	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLS6_P			0x00000006	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLS7_P			0x00000007	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
#define FLG1_P			0x00000009	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ 
#define FLG2_P			0x0000000A	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLG3_P			0x0000000B	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ 
#define FLG4_P			0x0000000C	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ 
#define FLG5_P			0x0000000D	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ 
#define FLG6_P			0x0000000E	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ 
#define FLG7_P			0x0000000F	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */

/* AMGCTL Masks */
#define AMCKEN			0x00000001	/* Enable CLKOUT */
#define AMBEN_B4		0x00000002	/* Enable Asynchronous Memory Bank 6 only */
#define AMBEN_B4_B5		0x00000004	/* Enable Asynchronous Memory Banks 4 & 5 only */
#define AMBEN_ALL		0x00000006	/* Enable Asynchronous Memory Banks (all) 4, 5, 6, and 7 */
#define B4PEN			0x00000010	/* Enable 16-bit packing for Asynchronous Memory Bank 4 */
#define B5PEN			0x00000020	/* Enable 16-bit packing for Asynchronous Memory Bank 5 */
#define B6PEN			0x00000040	/* Enable 16-bit packing for Asynchronous Memory Bank 6 */
#define B7PEN			0x00000080	/* Enable 16-bit packing for Asynchronous Memory Bank 7 */

/* AMGCTL Bit Positions */
#define AMCKEN_P		0x00000000	/* Enable CLKOUT */
#define AMBEN_P0		0x00000001	/* Asynchronous Memory Enable, 00 - banks 4-7 disabled, 01 - bank 4 enabled */
#define AMBEN_P1		0x00000002	/* Asynchronous Memory Enable, 10 - banks 4&5 enabled,  11 - banks 4-7 enabled */
#define B4PEN_P			0x00000004	/* Enable 16-bit packing for Asynchronous Memory Bank 4 */
#define B5PEN_P			0x00000005	/* Enable 16-bit packing for Asynchronous Memory Bank 5 */
#define B6PEN_P			0x00000006	/* Enable 16-bit packing for Asynchronous Memory Bank 6 */
#define B7PEN_P			0x00000007	/* Enable 16-bit packing for Asynchronous Memory Bank 7 */

/* AMBCTL0 Masks */
#define B4RDYEN			0x00000001	/* Bank 4 RDY Enable, 0=disable, 1=enable */
#define B4RDYPOL		0x00000002	/* Bank 4 RDY Active high, 0=active low, 1=active high */
#define B4TT_1			0x00000004	/* Bank 4 Transition Time from Read to Write = 1 cycle */
#define B4TT_2			0x00000008	/* Bank 4 Transition Time from Read to Write = 2 cycles */
#define B4TT_3			0x0000000C	/* Bank 4 Transition Time from Read to Write = 3 cycles */
#define B4TT_4			0x00000000	/* Bank 4 Transition Time from Read to Write = 4 cycles */
#define B4ST_1			0x00000010	/* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
#define B4ST_2			0x00000020	/* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
#define B4ST_3			0x00000030	/* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
#define B4ST_4			0x00000000	/* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
#define B4HT_1			0x00000040	/* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
#define B4HT_2			0x00000080	/* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
#define B4HT_3			0x000000C0	/* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
#define B4HT_4			0x00000000	/* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
#define B4RAT_1			0x00000100	/* Bank 4 Read Access Time = 1 cycle */
#define B4RAT_2			0x00000200	/* Bank 4 Read Access Time = 2 cycles */
#define B4RAT_3			0x00000300	/* Bank 4 Read Access Time = 3 cycles */
#define B4RAT_4			0x00000400	/* Bank 4 Read Access Time = 4 cycles */
#define B4RAT_5			0x00000500	/* Bank 4 Read Access Time = 5 cycles */
#define B4RAT_6			0x00000600	/* Bank 4 Read Access Time = 6 cycles */
#define B4RAT_7			0x00000700	/* Bank 4 Read Access Time = 7 cycles */
#define B4RAT_8			0x00000800	/* Bank 4 Read Access Time = 8 cycles */
#define B4RAT_9			0x00000900	/* Bank 4 Read Access Time = 9 cycles */
#define B4RAT_10		0x00000A00	/* Bank 4 Read Access Time = 10 cycles */
#define B4RAT_11		0x00000B00	/* Bank 4 Read Access Time = 11 cycles */
#define B4RAT_12		0x00000C00	/* Bank 4 Read Access Time = 12 cycles */
#define B4RAT_13		0x00000D00	/* Bank 4 Read Access Time = 13 cycles */
#define B4RAT_14		0x00000E00	/* Bank 4 Read Access Time = 14 cycles */
#define B4RAT_15		0x00000F00	/* Bank 4 Read Access Time = 15 cycles */
#define B4WAT_1			0x00001000	/* Bank 4 Write Access Time = 1 cycle */
#define B4WAT_2			0x00002000	/* Bank 4 Write Access Time = 2 cycles */
#define B4WAT_3			0x00003000	/* Bank 4 Write Access Time = 3 cycles */
#define B4WAT_4			0x00004000	/* Bank 4 Write Access Time = 4 cycles */
#define B4WAT_5			0x00005000	/* Bank 4 Write Access Time = 5 cycles */
#define B4WAT_6			0x00006000	/* Bank 4 Write Access Time = 6 cycles */
#define B4WAT_7			0x00007000	/* Bank 4 Write Access Time = 7 cycles */
#define B4WAT_8			0x00008000	/* Bank 4 Write Access Time = 8 cycles */
#define B4WAT_9			0x00009000	/* Bank 4 Write Access Time = 9 cycles */
#define B4WAT_10		0x0000A000	/* Bank 4 Write Access Time = 10 cycles */
#define B4WAT_11		0x0000B000	/* Bank 4 Write Access Time = 11 cycles */
#define B4WAT_12		0x0000C000	/* Bank 4 Write Access Time = 12 cycles */
#define B4WAT_13		0x0000D000	/* Bank 4 Write Access Time = 13 cycles */
#define B4WAT_14		0x0000E000	/* Bank 4 Write Access Time = 14 cycles */
#define B4WAT_15		0x0000F000	/* Bank 4 Write Access Time = 15 cycles */
#define B5RDYEN			0x00000001	/* Bank 5 RDY enable, 0=disable, 1=enable */
#define B5RDYPOL		0x00000002	/* Bank 5 RDY Active high, 0=active low, 1=active high */
#define B5TT_1			0x00000004	/* Bank 5 Transition Time from Read to Write = 1 cycle */
#define B5TT_2			0x00000008	/* Bank 5 Transition Time from Read to Write = 2 cycles */
#define B5TT_3			0x0000000C	/* Bank 5 Transition Time from Read to Write = 3 cycles */
#define B5TT_4			0x00000000	/* Bank 5 Transition Time from Read to Write = 4 cycles */
#define B5ST_1			0x00000010	/* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
#define B5ST_2			0x00000020	/* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
#define B5ST_3			0x00000030	/* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
#define B5ST_4			0x00000000	/* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
#define B5HT_1			0x00000040	/* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
#define B5HT_2			0x00000080	/* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
#define B5HT_3			0x000000C0	/* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
#define B5HT_4			0x00000000	/* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
#define B5RAT_1			0x00000100	/* Bank 5 Read Access Time = 1 cycle */
#define B5RAT_2			0x00000200	/* Bank 5 Read Access Time = 2 cycles */
#define B5RAT_3			0x00000300	/* Bank 5 Read Access Time = 3 cycles */
#define B5RAT_4			0x00000400	/* Bank 5 Read Access Time = 4 cycles */
#define B5RAT_5			0x00000500	/* Bank 5 Read Access Time = 5 cycles */
#define B5RAT_6			0x00000600	/* Bank 5 Read Access Time = 6 cycles */
#define B5RAT_7			0x00000700	/* Bank 5 Read Access Time = 7 cycles */
#define B5RAT_8			0x00000800	/* Bank 5 Read Access Time = 8 cycles */
#define B5RAT_9			0x00000900	/* Bank 5 Read Access Time = 9 cycles */
#define B5RAT_10		0x00000A00	/* Bank 5 Read Access Time = 10 cycles */
#define B5RAT_11		0x00000B00	/* Bank 5 Read Access Time = 11 cycles */
#define B5RAT_12		0x00000C00	/* Bank 5 Read Access Time = 12 cycles */
#define B5RAT_13		0x00000D00	/* Bank 5 Read Access Time = 13 cycles */
#define B5RAT_14		0x00000E00	/* Bank 5 Read Access Time = 14 cycles */
#define B5RAT_15		0x00000F00	/* Bank 5 Read Access Time = 15 cycles */
#define B5WAT_1			0x00001000	/* Bank 5 Write Access Time = 1 cycle */
#define B5WAT_2			0x00002000	/* Bank 5 Write Access Time = 2 cycles */
#define B5WAT_3			0x00003000	/* Bank 5 Write Access Time = 3 cycles */
#define B5WAT_4			0x00004000	/* Bank 5 Write Access Time = 4 cycles */
#define B5WAT_5			0x00005000	/* Bank 5 Write Access Time = 5 cycles */
#define B5WAT_6			0x00006000	/* Bank 5 Write Access Time = 6 cycles */
#define B5WAT_7			0x00007000	/* Bank 5 Write Access Time = 7 cycles */
#define B5WAT_8			0x00008000	/* Bank 5 Write Access Time = 8 cycles */
#define B5WAT_9			0x00009000	/* Bank 5 Write Access Time = 9 cycles */
#define B5WAT_10		0x0000A000	/* Bank 5 Write Access Time = 10 cycles */
#define B5WAT_11		0x0000B000	/* Bank 5 Write Access Time = 11 cycles */
#define B5WAT_12		0x0000C000	/* Bank 5 Write Access Time = 12 cycles */
#define B5WAT_13		0x0000D000	/* Bank 5 Write Access Time = 13 cycles */
#define B5WAT_14		0x0000E000	/* Bank 5 Write Access Time = 14 cycles */
#define B5WAT_15		0x0000F000	/* Bank 5 Write Access Time = 15 cycles */

/* AMBCTL1 Masks */
#define B6RDYEN			0x00000001	/* Bank 6 RDY Enable, 0=disable, 1=enable */
#define B6RDYPOL		0x00000002	/* Bank 6 RDY Active high, 0=active low, 1=active high */
#define B6TT_1			0x00000004	/* Bank 6 Transition Time from Read to Write = 1 cycle */
#define B6TT_2			0x00000008	/* Bank 6 Transition Time from Read to Write = 2 cycles */
#define B6TT_3			0x0000000C	/* Bank 6 Transition Time from Read to Write = 3 cycles */
#define B6TT_4			0x00000000	/* Bank 6 Transition Time from Read to Write = 4 cycles */
#define B6ST_1			0x00000010	/* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
#define B6ST_2			0x00000020	/* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
#define B6ST_3			0x00000030	/* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
#define B6ST_4			0x00000000	/* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
#define B6HT_1			0x00000040	/* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
#define B6HT_2			0x00000080	/* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
#define B6HT_3			0x000000C0	/* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
#define B6HT_4			0x00000000	/* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
#define B6RA