defbf535.h

此代码实现blackfin系列DSP的上电监控代码

/*
 * defBF535.h
 *
 * This file is subject to the terms and conditions of the GNU Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Non-GPL License also available as part of VisualDSP++
 *
 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
 *
 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
 *
 * This file under source code control, please send bugs or changes to:
 * [e-mail]
 *
 */

/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF535 */

#ifndef _DEF_BF535_H
#define _DEF_BF535_H

#if defined(__ADSPLPBLACKFIN__)
	#warning defBF535.h should only be included for 535 compatible chips.
#endif

/* include all Core registers and bit definitions */
#include <defBlackfin.h>

/*
 * Memory Map
 */

/* Core MMRs */
#define COREMMR_BASE		0xFFE00000	/* Core MMRs */
#define COREMMR_SIZE		0x200000	/* 2MB */

/* System MMRs */
#define SYSMMR_BASE		0xFFC00000	/* System MMRs */
#define SYSMMR_SIZE		0x200000	/* 2MB */

/* L1 cache/SRAM internal memory */
#define L1_DATA_A		0xFF800000	/* L1 Data Bank A */
#define L1_DATA_B		0xFF900000	/* L1 Data Bank B */
#define L1_DATA_SIZE		0x4000		/*  16K */
#define L1_CODE			0xFFA00000	/* L1 Code SRAM */
#define L1_CODE_SIZE		0x4000		/*  16K */
#define L1_SCRATCH		0xFFB00000	/* L1 Scratch SRAM */
#define L1_SCRATCH_SIZE		0x1000		/*  4K */

/* L2 SRAM external memory */
#define L2_BASE			0xF0000000	/* L2 SRAM */
#define L2_SIZE			0x40000		/* 256K */

/* PCI Spaces */
#define PCI_CONFIG_SPACE_PORT	0xEEFFFFFC	/* PCI config space reg */
#define PCI_CONFIG_BASE		0xEEFFFF00	/* PCI config region */
#define PCI_CONFIG_SIZE		0x10000		/*  64K */
#define PCI_IO_BASE		0xEEFE0000	/* PCI I/O space */
#define PCI_IO_SIZE		0x10000		/*  64K */
#define PCI_MEM_BASE		0xE0000000	/* PCI Mem space */
#define PCI_MEM_SIZE		0x8000000	/*  64K */

/* Async Memory Banks */
#define ASYNC_BANK3_BASE	0x2C000000	/* Async Bank 3 */
#define ASYNC_BANK3_SIZE	0x4000000	/*  64 MB */
#define ASYNC_BANK2_BASE	0x28000000	/* Async Bank 2 */
#define ASYNC_BANK2_SIZE	0x4000000	/*  64 MB */
#define ASYNC_BANK1_BASE	0x24000000	/* Async Bank 1 */
#define ASYNC_BANK1_SIZE	0x4000000	/*  64 MB */
#define ASYNC_BANK0_BASE	0x20000000	/* Async Bank 0 */
#define ASYNC_BANK0_SIZE	0x4000000	/*  64 MB */

/* Sync DRAM Banks */
#define SDRAM_BANK3_BASE	0x18000000	/* Sync Bank 3 */
#define SDRAM_BANK2_BASE	0x10000000	/* Sync Bank 2 */
#define SDRAM_BANK1_BASE	0x08000000	/* Sync Bank 1 */
#define SDRAM_BANK0_BASE	0x00000000	/* Sync Bank 0 */

/*
 * System MMR Register Map
 */

/* L2 MISR MMRs (0xFFC0 0000-0xFFC0 03FF) */
#define MISR_CTL		0xFFC00000	/* Control Register */
#define MISR_RMISR0		0xFFC00004	/* coreL2[31:0] read bus */
#define MISR_RMISR1		0xFFC00008	/* coreL2[63:32] read bus */
#define MISR_RMISR2		0xFFC0000C	/* sysL2[31:0] read bus */
#define MISR_WMISR0		0xFFC00010	/* coreL2[31:0] write bus */
#define MISR_WMISR1		0xFFC00014	/* coreL2[63:32] write bus */
#define MISR_WMISR2		0xFFC00018	/* sysL2[31:0] write bus */

/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
#define PLL_CTL			0xFFC00400	/* PLL Control register (32-bit) */
#define PLL_STAT		0xFFC00404	/* PLL Status register */
#define PLL_LOCKCNT		0xFFC00406	/* PLL Lock Counter register */
#define PLL_IOCKR		0xFFC00408	/* Peripheral Clock Enable register (32-bit) */
#define SWRST			0xFFC00410	/* Software Reset Register */

#define PLLCTL			PLL_CTL
#define PLLSTAT			PLL_STAT
#define LOCKCNT			PLL_LOCKCNT
#define IOCKR			PLL_IOCKR

#define SYSCR			0xFFC00414	/* System Configuration register (RCSR) */

/* JTAG/Debug Communication Channel (0xFFC0 0800-0xFFC0 0BFF) */
#define CHIPID			0xFFC048C0	/* Device ID Register */

/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
#define SIC_RVECT		0xFFC00C00	/* Reset Vector Register */
#define SIC_IAR0		0xFFC00C04	/* Interrupt Assignment Register 0 */
#define SIC_IAR1		0xFFC00C08	/* Interrupt Assignment Register 1 */
#define SIC_IAR2		0xFFC00C0C	/* Interrupt Assignment Register 2 */
#define SIC_IMASK		0xFFC00C10	/* Interrupt Mask Register */
#define SIC_ISR			0xFFC00C14	/* Interrupt Status Register */
#define SIC_IWR			0xFFC00C18	/* Interrupt Wakeup Register */

/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
#define WDOGCTL			0xFFC01000	/* Watchdog Control Register */
#define WDOGCNT			0xFFC01004	/* Watchdog Count Register */
#define WDOGSTAT		0xFFC01008	/* Watchdog Status Register */

#define WDOG_CTL		WDOGCTL
#define WDOG_CNT		WDOGCNT
#define WDOG_STAT		WDOGSTAT

/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
#define RTCSTAT			0xFFC01400	/* RTC Status Register */
#define RTCICTL			0xFFC01404	/* RTC Interrupt Control Register */
#define RTCISTAT		0xFFC01408	/* RTC Interrupt Status Register */
#define RTCSWCNT		0xFFC0140C	/* RTC Stopwatch Count Register */
#define RTCALARM		0xFFC01410	/* RTC Alarm Time Register */
#define RTCFAST			0xFFC01414	/* RTC Prescaler Control Register */

#define RTC_STAT		RTCSTAT
#define RTC_ICTL		RTCICTL
#define RTC_ISTAT		RTCISTAT
#define RTC_SWCNT		RTCSWCNT
#define RTC_ALARM		RTCALARM
#define RTC_FAST		RTCFAST

/* UART 0 Controller (0xFFC0 1800-0xFFC0 1BFF) */
#define UART0_THR		0xFFC01800	/* Transmit Holding register */
#define UART0_RBR		0xFFC01800	/* Receive Buffer register */
#define UART0_DLL		0xFFC01800	/* Divisor Latch (Low-Byte) */
#define UART0_IER		0xFFC01802	/* Interrupt Enable Register */
#define UART0_DLH		0xFFC01802	/* Divisor Latch (High-Byte) */
#define UART0_IIR		0xFFC01804	/* Interrupt Identification Register */
#define UART0_LCR		0xFFC01806	/* Line Control Register */
#define UART0_MCR		0xFFC01808	/* Module Control Register */
#define UART0_LSR		0xFFC0180A	/* Line Status Register */
#define UART0_MSR		0xFFC0180C	/* MSR Modem Status Register */
#define UART0_SCR		0xFFC0180E	/* SCR Scratch Register */
#define UART0_IRCR		0xFFC01810	/* IRCR IrDA Control Register */
#define UART0_CURR_PTR_RX	0xFFC01A00	/* UART -DMA RCV Current Pointer register */
#define UART0_CONFIG_RX		0xFFC01A02	/* UART -RCV DMA Configuration register */
#define UART0_START_ADDR_HI_RX	0xFFC01A04	/* UART -RCV DMA Start Page register */
#define UART0_START_ADDR_LO_RX	0xFFC01A06	/* UART -RCV DMA Start Address register */
#define UART0_COUNT_RX		0xFFC01A08	/* UART -RCV DMA Count register */
#define UART0_NEXT_DESCR_RX	0xFFC01A0A	/* UART -RCV DMA Next Descriptor Pointer register */
#define UART0_DESCR_RDY_RX	0xFFC01A0C	/* UART -RCV DMA Descriptor Ready */
#define UART0_IRQSTAT_RX	0xFFC01A0E	/* UART -RCV DMA Interrupt Register */
#define UART0_CURR_PTR_TX	0xFFC01B00	/* UART -XMT DMA Current Pointer register */
#define UART0_CONFIG_TX		0xFFC01B02	/* UART -XMT DMA Configuration register */
#define UART0_START_ADDR_HI_TX	0xFFC01B04	/* UART -XMT DMA Start Page register */
#define UART0_START_ADDR_LO_TX 	0xFFC01B06	/* UART -XMT DMA Start Address register */
#define UART0_COUNT_TX		0xFFC01B08	/* UART -XMT DMA Count register */
#define UART0_NEXT_DESCR_TX	0xFFC01B0A	/* UART -XMT DMA Next Descriptor Pointer register */
#define UART0_DESCR_RDY_TX	0xFFC01B0C	/* UART -XMT DMA Descriptor Ready */
#define UART0_IRQSTAT_TX	0xFFC01B0E	/* UART -XMT DMA Interrupt register */

/* UART 1 Controller (0xFFC0 1C00-0xFFC0 1FFF) */
#define UART1_THR		0xFFC01C00	/* Transmit Holding register */
#define UART1_RBR		0xFFC01C00	/* Receive Buffer register */
#define UART1_DLL		0xFFC01C00	/* Divisor Latch (Low-Byte) */
#define UART1_IER		0xFFC01C02	/* Interrupt Enable Register */
#define UART1_DLH		0xFFC01C02	/* Divisor Latch (High-Byte) */
#define UART1_IIR		0xFFC01C04	/* Interrupt Identification Register */
#define UART1_LCR		0xFFC01C06	/* Line Control Register */
#define UART1_MCR		0xFFC01C08	/* Module Control Register */
#define UART1_LSR		0xFFC01C0A	/* Line Status Register */
#define UART1_MSR		0xFFC01C0C	/* MSR Modem Status Register */
#define UART1_SCR		0xFFC01C0E	/* SCR Scratch Register */
#define UART1_CURR_PTR_RX	0xFFC01E00	/* UART -DMA RCV Current Pointer register */
#define UART1_CONFIG_RX		0xFFC01E02	/* UART -RCV DMA Configuration register */
#define UART1_START_ADDR_HI_RX	0xFFC01E04	/* UART -RCV DMA Start Page register */
#define UART1_START_ADDR_LO_RX	0xFFC01E06	/* UART -RCV DMA Start Address register */
#define UART1_COUNT_RX		0xFFC01E08	/* UART -RCV DMA Count register */
#define UART1_NEXT_DESCR_RX	0xFFC01E0A	/* UART -RCV DMA Next Descriptor Pointer register */
#define UART1_DESCR_RDY_RX	0xFFC01E0C	/* UART -RCV DMA Descriptor Ready */
#define UART1_IRQSTAT_RX	0xFFC01E0E	/* UART -RCV DMA Interrupt Register */
#define UART1_CURR_PTR_TX	0xFFC01F00	/* UART -XMT DMA Current Pointer register */
#define UART1_CONFIG_TX		0xFFC01F02	/* UART -XMT DMA Configuration register */
#define UART1_START_ADDR_HI_TX	0xFFC01F04	/* UART -XMT DMA Start Page register */
#define UART1_START_ADDR_LO_TX	0xFFC01F06	/* UART -XMT DMA Start Address register */
#define UART1_COUNT_TX		0xFFC01F08	/* UART -XMT DMA Count register */
#define UART1_NEXT_DESCR_TX	0xFFC01F0A	/* UART -XMT DMA Next Descriptor Pointer register */
#define UART1_DESCR_RDY_TX	0xFFC01F0C	/* UART -XMT DMA Descriptor Ready */
#define UART1_IRQSTAT_TX	0xFFC01F0E	/* UART -XMT DMA Interrupt register */

/* TIMER 0, 1, 2 Registers (0xFFC0 2000-0xFFC0 23FF) */
#define TIMER0_STATUS		0xFFC02000	/* Timer 0 Global Status and Sticky Register */
#define TIMER0_CONFIG		0xFFC02002	/* Timer 0 configuration Register */
#define TIMER0_COUNTER_LO	0xFFC02004	/* Timer 0 Counter Register (low word) */
#define TIMER0_COUNTER_HI	0xFFC02006	/* Timer 0 Counter Register (high word) */
#define TIMER0_PERIOD_LO	0xFFC02008	/* Timer 0 Period Register (low word) */
#define TIMER0_PERIOD_HI	0xFFC0200A	/* Timer 0 Period Register (high word) */
#define TIMER0_WIDTH_LO		0xFFC0200C	/* Timer 0 Width Register (low word) */
#define TIMER0_WIDTH_HI		0xFFC0200E	/* Timer 0 Width Register (high word) */
#define TIMER1_STATUS		0xFFC02010	/* Timer 1 Global Status and Sticky Register */
#define TIMER1_CONFIG		0xFFC02012	/* Timer 1 configuration register */
#define TIMER1_COUNTER_LO	0xFFC02014	/* Timer 1 Counter Register (low word) */