defbf561.h

此代码实现blackfin系列DSP的上电监控代码

#define DMA2_0_CURR_ADDR	0xFFC00C24	// DMA2 Channel 0 Current
						// Address Pointer
#define DMA2_0_CURR_X_COUNT	0xFFC00C30	// DMA2 Channel 0 Current Inner
						// Loop Count
#define DMA2_0_CURR_Y_COUNT	0xFFC00C38	// DMA2 Channel 0 Current Outer
						// Loop Count
#define DMA2_0_IRQ_STATUS	0xFFC00C28	// DMA2 Channel 0 Interrupt
						// /Status Register
#define DMA2_0_PERIPHERAL_MAP	0xFFC00C2C	// DMA2 Channel 0 Peripheral
						// Map Register

#define DMA2_1_CONFIG		0xFFC00C48	// DMA2 Channel 1 Configuration
						// register
#define DMA2_1_NEXT_DESC_PTR	0xFFC00C40	// DMA2 Channel 1 Next
						// Descripter Ptr Reg
#define DMA2_1_START_ADDR	0xFFC00C44	// DMA2 Channel 1 Start Address
#define DMA2_1_X_COUNT		0xFFC00C50	// DMA2 Channel 1 Inner Loop
						// Count
#define DMA2_1_Y_COUNT		0xFFC00C58	// DMA2 Channel 1 Outer Loop
						// Count
#define DMA2_1_X_MODIFY		0xFFC00C54	// DMA2 Channel 1 Inner Loop
						// Addr Increment
#define DMA2_1_Y_MODIFY		0xFFC00C5C	// DMA2 Channel 1 Outer Loop
						// Addr Increment
#define DMA2_1_CURR_DESC_PTR	0xFFC00C60	// DMA2 Channel 1 Current
						// Descriptor Pointer
#define DMA2_1_CURR_ADDR	0xFFC00C64	// DMA2 Channel 1 Current
						// Address Pointer
#define DMA2_1_CURR_X_COUNT	0xFFC00C70	// DMA2 Channel 1 Current
						// Inner Loop Count
#define DMA2_1_CURR_Y_COUNT	0xFFC00C78	// DMA2 Channel 1 Current
						// Outer Loop Count
#define DMA2_1_IRQ_STATUS	0xFFC00C68	// DMA2 Channel 1 Interrupt
						// /Status Register
#define DMA2_1_PERIPHERAL_MAP	0xFFC00C6C	// DMA2 Channel 1 Peripheral
						// Map Register

#define DMA2_2_CONFIG		0xFFC00C88	// DMA2 Channel 2 Configuration
						// register
#define DMA2_2_NEXT_DESC_PTR	0xFFC00C80	// DMA2 Channel 2 Next
						// Descripter Ptr Reg
#define DMA2_2_START_ADDR	0xFFC00C84	// DMA2 Channel 2 Start Address
#define DMA2_2_X_COUNT		0xFFC00C90	// DMA2 Channel 2 Inner Loop
						// Count
#define DMA2_2_Y_COUNT		0xFFC00C98	// DMA2 Channel 2 Outer Loop
						// Count
#define DMA2_2_X_MODIFY		0xFFC00C94	// DMA2 Channel 2 Inner Loop
						// Addr Increment
#define DMA2_2_Y_MODIFY		0xFFC00C9C	// DMA2 Channel 2 Outer Loop
						// Addr Increment
#define DMA2_2_CURR_DESC_PTR	0xFFC00CA0	// DMA2 Channel 2 Current
						// Descriptor Pointer
#define DMA2_2_CURR_ADDR	0xFFC00CA4	// DMA2 Channel 2 Current
						// Address Pointer
#define DMA2_2_CURR_X_COUNT	0xFFC00CB0	// DMA2 Channel 2 Current Inner
						// Loop Count
#define DMA2_2_CURR_Y_COUNT	0xFFC00CB8	// DMA2 Channel 2 Current Outer
						// Loop Count
#define DMA2_2_IRQ_STATUS	0xFFC00CA8	// DMA2 Channel 2 Interrupt
						// /Status Register
#define DMA2_2_PERIPHERAL_MAP	0xFFC00CAC	// DMA2 Channel 2 Peripheral
						// Map Register

#define DMA2_3_CONFIG		0xFFC00CC8	// DMA2 Channel 3 Configuration
						// register
#define DMA2_3_NEXT_DESC_PTR	0xFFC00CC0	// DMA2 Channel 3 Next
						// Descripter Ptr Reg
#define DMA2_3_START_ADDR	0xFFC00CC4	// DMA2 Channel 3 Start Address
#define DMA2_3_X_COUNT		0xFFC00CD0	// DMA2 Channel 3 Inner Loop
						// Count
#define DMA2_3_Y_COUNT		0xFFC00CD8	// DMA2 Channel 3 Outer Loop
						// Count
#define DMA2_3_X_MODIFY		0xFFC00CD4	// DMA2 Channel 3 Inner Loop
						// Addr Increment
#define DMA2_3_Y_MODIFY		0xFFC00CDC	// DMA2 Channel 3 Outer Loop
						// Addr Increment
#define DMA2_3_CURR_DESC_PTR	0xFFC00CE0	// DMA2 Channel 3 Current
						// Descriptor Pointer
#define DMA2_3_CURR_ADDR	0xFFC00CE4	// DMA2 Channel 3 Current
						// Address Pointer
#define DMA2_3_CURR_X_COUNT	0xFFC00CF0	// DMA2 Channel 3 Current Inner
						// Loop Count
#define DMA2_3_CURR_Y_COUNT	0xFFC00CF8	// DMA2 Channel 3 Current Outer
						// Loop Count
#define DMA2_3_IRQ_STATUS	0xFFC00CE8	// DMA2 Channel 3 Interrupt
						// /Status Register
#define DMA2_3_PERIPHERAL_MAP	0xFFC00CEC	// DMA2 Channel 3 Peripheral
						// Map Register

#define DMA2_4_CONFIG		0xFFC00D08	// DMA2 Channel 4 Configuration
						// register
#define DMA2_4_NEXT_DESC_PTR	0xFFC00D00	// DMA2 Channel 4 Next
						// Descripter Ptr Reg
#define DMA2_4_START_ADDR	0xFFC00D04	// DMA2 Channel 4 Start Address
#define DMA2_4_X_COUNT		0xFFC00D10	// DMA2 Channel 4 Inner Loop
						// Count
#define DMA2_4_Y_COUNT		0xFFC00D18	// DMA2 Channel 4 Outer Loop
						// Count
#define DMA2_4_X_MODIFY		0xFFC00D14	// DMA2 Channel 4 Inner Loop
						// Addr Increment
#define DMA2_4_Y_MODIFY		0xFFC00D1C	// DMA2 Channel 4 Outer Loop
						// Addr Increment
#define DMA2_4_CURR_DESC_PTR	0xFFC00D20	// DMA2 Channel 4 Current
						// Descriptor Pointer
#define DMA2_4_CURR_ADDR	0xFFC00D24	// DMA2 Channel 4 Current
						// Address Pointer
#define DMA2_4_CURR_X_COUNT	0xFFC00D30	// DMA2 Channel 4 Current Inner
						// Loop Count
#define DMA2_4_CURR_Y_COUNT	0xFFC00D38	// DMA2 Channel 4 Current Outer
						// Loop Count
#define DMA2_4_IRQ_STATUS	0xFFC00D28	// DMA2 Channel 4 Interrupt
						// /Status Register
#define DMA2_4_PERIPHERAL_MAP	0xFFC00D2C	// DMA2 Channel 4 Peripheral
						// Map Register

#define DMA2_5_CONFIG		0xFFC00D48	// DMA2 Channel 5 Configuration
						// register
#define DMA2_5_NEXT_DESC_PTR	0xFFC00D40	// DMA2 Channel 5 Next
						// Descripter Ptr Reg
#define DMA2_5_START_ADDR	0xFFC00D44	// DMA2 Channel 5 Start Address
#define DMA2_5_X_COUNT		0xFFC00D50	// DMA2 Channel 5 Inner Loop
						// Count
#define DMA2_5_Y_COUNT		0xFFC00D58	// DMA2 Channel 5 Outer Loop
						// Count
#define DMA2_5_X_MODIFY		0xFFC00D54	// DMA2 Channel 5 Inner Loop
						// Addr Increment
#define DMA2_5_Y_MODIFY		0xFFC00D5C	// DMA2 Channel 5 Outer Loop
						// Addr Increment
#define DMA2_5_CURR_DESC_PTR	0xFFC00D60	// DMA2 Channel 5 Current
						// Descriptor Pointer
#define DMA2_5_CURR_ADDR	0xFFC00D64	// DMA2 Channel 5 Current
						// Address Pointer
#define DMA2_5_CURR_X_COUNT	0xFFC00D70	// DMA2 Channel 5 Current Inner
						// Loop Count
#define DMA2_5_CURR_Y_COUNT	0xFFC00D78	// DMA2 Channel 5 Current Outer
						// Loop Count
#define DMA2_5_IRQ_STATUS	0xFFC00D68	// DMA2 Channel 5 Interrupt
						// /Status Register
#define DMA2_5_PERIPHERAL_MAP	0xFFC00D6C	// DMA2 Channel 5 Peripheral
						// Map Register

#define DMA2_6_CONFIG		0xFFC00D88	// DMA2 Channel 6 Configuration
						// register
#define DMA2_6_NEXT_DESC_PTR	0xFFC00D80	// DMA2 Channel 6 Next
						// Descripter Ptr Reg
#define DMA2_6_START_ADDR	0xFFC00D84	// DMA2 Channel 6 Start Address
#define DMA2_6_X_COUNT		0xFFC00D90	// DMA2 Channel 6 Inner Loop
						// Count
#define DMA2_6_Y_COUNT		0xFFC00D98	// DMA2 Channel 6 Outer Loop
						// Count
#define DMA2_6_X_MODIFY		0xFFC00D94	// DMA2 Channel 6 Inner Loop
						// Addr Increment
#define DMA2_6_Y_MODIFY		0xFFC00D9C	// DMA2 Channel 6 Outer Loop
						// Addr Increment
#define DMA2_6_CURR_DESC_PTR	0xFFC00DA0	// DMA2 Channel 6 Current
						// Descriptor Pointer
#define DMA2_6_CURR_ADDR	0xFFC00DA4	// DMA2 Channel 6 Current
						// Address Pointer
#define DMA2_6_CURR_X_COUNT	0xFFC00DB0	// DMA2 Channel 6 Current Inner
						// Loop Count
#define DMA2_6_CURR_Y_COUNT	0xFFC00DB8	// DMA2 Channel 6 Current Outer
						// Loop Count
#define DMA2_6_IRQ_STATUS	0xFFC00DA8	// DMA2 Channel 6 Interrupt
						// /Status Register
#define DMA2_6_PERIPHERAL_MAP	0xFFC00DAC	// DMA2 Channel 6 Peripheral
						// Map Register

#define DMA2_7_CONFIG		0xFFC00DC8	// DMA2 Channel 7 Configuration
						// register
#define DMA2_7_NEXT_DESC_PTR	0xFFC00DC0	// DMA2 Channel 7 Next
						// Descripter Ptr Reg
#define DMA2_7_START_ADDR	0xFFC00DC4	// DMA2 Channel 7 Start Address
#define DMA2_7_X_COUNT		0xFFC00DD0	// DMA2 Channel 7 Inner Loop
						// Count
#define DMA2_7_Y_COUNT		0xFFC00DD8	// DMA2 Channel 7 Outer Loop
						// Count
#define DMA2_7_X_MODIFY		0xFFC00DD4	// DMA2 Channel 7 Inner Loop
						// Addr Increment
#define DMA2_7_Y_MODIFY		0xFFC00DDC	// DMA2 Channel 7 Outer Loop
						// Addr Increment
#define DMA2_7_CURR_DESC_PTR	0xFFC00DE0	// DMA2 Channel 7 Current
						// Descriptor Pointer
#define DMA2_7_CURR_ADDR	0xFFC00DE4	// DMA2 Channel 7 Current
						// Address Pointer
#define DMA2_7_CURR_X_COUNT	0xFFC00DF0	// DMA2 Channel 7 Current Inner
						// Loop Count
#define DMA2_7_CURR_Y_COUNT	0xFFC00DF8	// DMA2 Channel 7 Current Outer
						// Loop Count
#define DMA2_7_IRQ_STATUS	0xFFC00DE8	// DMA2 Channel 7 Interrupt
						// /Status Register
#define DMA2_7_PERIPHERAL_MAP	0xFFC00DEC	// DMA2 Channel 7 Peripheral
						// Map Register

#define DMA2_8_CONFIG		0xFFC00E08	// DMA2 Channel 8 Configuration
						// register
#define DMA2_8_NEXT_DESC_PTR	0xFFC00E00	// DMA2 Channel 8 Next
						// Descripter Ptr Reg
#define DMA2_8_START_ADDR	0xFFC00E04	// DMA2 Channel 8 Start Address
#define DMA2_8_X_COUNT		0xFFC00E10	// DMA2 Channel 8 Inner Loop
						// Count
#define DMA2_8_Y_COUNT		0xFFC00E18	// DMA2 Channel 8 Outer Loop
						// Count
#define DMA2_8_X_MODIFY		0xFFC00E14	// DMA2 Channel 8 Inner Loop
						// Addr Increment
#define DMA2_8_Y_MODIFY		0xFFC00E1C	// DMA2 Channel 8 Outer Loop
						// Addr Increment
#define DMA2_8_CURR_DESC_PTR	0xFFC00E20	// DMA2 Channel 8 Current
						// Descriptor Pointer
#define DMA2_8_CURR_ADDR	0xFFC00E24	// DMA2 Channel 8 Current
						// Address Pointer
#define DMA2_8_CURR_X_COUNT	0xFFC00E30	// DMA2 Channel 8 Current Inner
						// Loop Count
#define DMA2_8_CURR_Y_COUNT	0xFFC00E38	// DMA2 Channel 8 Current Outer
						// Loop Count
#define DMA2_8_IRQ_STATUS	0xFFC00E28	// DMA2 Channel 8 Interrupt
						// /Status Register
#define DMA2_8_PERIPHERAL_MAP	0xFFC00E2C	// DMA2 Channel 8 Peripheral
						// Map Register

#define DMA2_9_CONFIG		0xFFC00E48	// DMA2 Channel 9 Configuration
						// register
#define DMA2_9_NEXT_DESC_PTR	0xFFC00E40	// DMA2 Channel 9 Next
						// Descripter Ptr Reg
#define DMA2_9_START_ADDR	0xFFC00E44	// DMA2 Channel 9 Start Address
#define DMA2_9_X_COUNT		0xFFC00E50	// DMA2 Channel 9 Inner Loop
						// Count
#define DMA2_9_Y_COUNT		0xFFC00E58	// DMA2 Channel 9 Outer Loop
						// Count
#define DMA2_9_X_MODIFY		0xFFC00E54	// DMA2 Channel 9 Inner Loop
						// Addr Increment
#define DMA2_9_Y_MODIFY		0xFFC00E5C	// DMA2 Channel 9 Outer Loop
						// Addr Increment
#define DMA2_9_CURR_DESC_PTR	0xFFC00E60	// DMA2 Channel 9 Current
						// Descriptor Pointer
#define DMA2_9_CURR_ADDR	0xFFC00E64	// DMA2 Channel 9 Current
						// Address Pointer
#define DMA2_9_CURR_X_COUNT	0xFFC00E70	// DMA2 Channel 9 Current Inner
						// Loop Count
#define DMA2_9_CURR_Y_COUNT	0xFFC00E78	// DMA2 Channel 9 Current Outer
						// Loop Count
#define DMA2_9_IRQ_STATUS	0xFFC00E68	// DMA2 Channel 9 Interrupt
						// /Status Register
#define DMA2_9_PERIPHERAL_MAP	0xFFC00E6C	// DMA2 Channel 9 Peripheral
						// Map Register

#define DMA2_10_CONFIG		0xFFC00E88	// DMA2 Channel 10 Configuration
						// register
#define DMA2_10_NEXT_DESC_PTR	0xFFC00E80	// DMA2 Channel 10 Next
						// Descripter Ptr Reg
#define DMA2_10_START_ADDR	0xFFC00E84	// DMA2 Channel 10 Start Address
#define DMA2_10_X_COUNT		0xFFC00E90	// DMA2 Channel 10 Inner Loop
						// Count
#define DMA2_10_Y_COUNT		0xFFC00E98	// DMA2 Channel 10 Outer Loop
						// Count
#define DMA2_10_X_MODIFY	0xFFC00E94	// DMA2 Channel 10 Inner Loop
						// Addr Increment
#define DMA2_10_Y_MODIFY	0xFFC00E9C	// DMA2 Channel 10 Outer Loop
						// Addr Increment
#define DMA2_10_CURR_DESC_PTR	0xFFC00EA0	// DMA2 Channel 10 Current
						// Descriptor Pointer
#define DMA2_10_CURR_ADDR	0xFFC00EA4	// DMA2 Channel 10 Current
						// Address Pointer
#define DMA2_10_CURR_X_COUNT	0xFFC00EB0	// DMA2 Channel 10 Current Inner
						// Loop Count
#define DMA2_10_CURR_Y_COUNT	0xFFC00EB8	// DMA2 Channel 10 Current Outer
						// Loop Count
#define DMA2_10_IRQ_STATUS	0xFFC00EA8	// DMA2 Channel 10 Interrupt
						// /Status Register
#define DMA2_10_PERIPHERAL_MAP	0xFFC00EAC	// DMA2 Channel 10 Peripheral 
						// Map Register

#define DMA2_11_CONFIG		0xFFC00EC8	// DMA2 Channel 11 Configuration
						// register
#define DMA2_11_NEXT_DESC_PTR	0xFFC00EC0	// DMA2 Channel 11 Next
						// Descripter Ptr Reg
#define DMA2_11_START_ADDR	0xFFC00EC4	// DMA2 Channel 11 Start Address
#define DMA2_11_X_COUNT		0xFFC00ED0	// DMA2 Channel 11 Inner Loop
						// Count
#define DMA2_11_Y_COUNT		0xFFC00ED8	// DMA2 Channel 11 Outer Loop
						// Count
#define DMA2_11_X_MODIFY	0xFFC00ED4	// DMA2 Channel 11 Inner Loop
						// Addr Increment
#define DMA2_11_Y_MODIFY	0xFFC00EDC	// DMA2 Channel 11 Outer Loop
						// Addr Increment
#define DMA2_11_CURR_DESC_PTR	0xFFC00EE0	// DMA2 Channel 11 Current
						// Descriptor Pointer
#define DMA2_11_CURR_ADDR	0xFFC00EE4	// DMA2 Channel 11 Current
						// Address Pointer
#define DMA2_11_CURR_X_COUNT	0xFFC00EF0	// DMA2 Channel 11 Current Inner
						// Loop Count
#define DMA2_11_CURR_Y_COUNT	0xFFC00EF8	// DMA2 Channel 11 Current Outer
						// Loop Count
#define DMA2_11_IRQ_STATUS	0xFFC00EE8	// DMA2 Channel 11 Interrupt