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;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen2)
;// <i> Selects the delay from CS2 to write enable
;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WWEN2_Val EQU 0x00000000
;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen2)
;// <i> Selects the delay from CS2 or address change, whichever is later, to output enable
;// <o.0..3> WAITOEN: Wait output enable <0-15>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WOEN2_Val EQU 0x00000000
;// <h> Static Memory Read Delay Register (EMCStaticWaitRd2)
;// <i> Selects the delay from CS2 to a read access
;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WRD2_Val EQU 0x0000001F
;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage2)
;// <i> Selects the delay for asynchronous page mode sequential accesses for CS2
;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WPAGE2_Val EQU 0x0000001F
;// <h> Static Memory Write Delay Register (EMCStaticWaitWr2)
;// <i> Selects the delay from CS2 to a write access
;// <o.0..4> WAITWR: Write wait states <2-33> <#-2>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WWR2_Val EQU 0x0000001F
;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn2)
;// <i> Selects the number of bus turnaround cycles for CS2
;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WTURN2_Val EQU 0x0000000F
;// </e> End of Static Setup for Static CS2 Area
;// Configure External Bus Behaviour for Static CS3 Area ---------------
;// <e> Configure External Bus Behaviour for Static CS3 Area
EMC_STACS3_SETUP EQU 0
;// <h> Static Memory Configuration Register (EMCStaticConfig3)
;// <i> Defines the configuration information for the static memory CS3
;// <o0.20> WP: Write protect
;// <o0.19> B: Buffer enable
;// <o0.8> EW: Extended wait enable
;// <o0.7> PB: Byte lane state
;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW
;// <1=> For reads BLSn are LOW, for writes BLSn are LOW
;// <o0.6> PC: Chip select polarity
;// <0=> Active LOW chip select
;// <1=> Active HIGH chip select
;// <o0.3> PM: Page mode enable
;// <o0.0..1> MW: Memory width
;// <0=> 8 bit
;// <1=> 16 bit
;// <2=> 32 bit
;// </h>
EMC_STA_CFG3_Val EQU 0x00000000
;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen3)
;// <i> Selects the delay from CS3 to write enable
;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WWEN3_Val EQU 0x00000000
;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen3)
;// <i> Selects the delay from CS3 or address change, whichever is later, to output enable
;// <o.0..3> WAITOEN: Wait output enable <0-15>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WOEN3_Val EQU 0x00000000
;// <h> Static Memory Read Delay Register (EMCStaticWaitRd3)
;// <i> Selects the delay from CS3 to a read access
;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WRD3_Val EQU 0x0000001F
;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage3)
;// <i> Selects the delay for asynchronous page mode sequential accesses for CS3
;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WPAGE3_Val EQU 0x0000001F
;// <h> Static Memory Write Delay Register (EMCStaticWaitWr3)
;// <i> Selects the delay from CS3 to a write access
;// <o.0..4> WAITWR: Write wait states <2-33> <#-2>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WWR3_Val EQU 0x0000001F
;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn3)
;// <i> Selects the number of bus turnaround cycles for CS3
;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
;// <i> The delay is in CCLK cycles
;// </h>
EMC_STA_WTURN3_Val EQU 0x0000000F
;// </e> End of Static Setup for Static CS3 Area
;// <h> Static Memory Extended Wait Register (EMCStaticExtendedWait)
;// <i> Time long static memory read and write transfers
;// <o.0..9> EXTENDEDWAIT: Extended wait time out <0-1023>
;// <i> The delay is in (16 * CCLK) cycles
;// </h>
EMC_STA_EXT_W_Val EQU 0x00000000
;// </e> End of Static Setup
;// </e> End of EMC Setup
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
; LDR PC, IRQ_Addr
LDR PC, [PC, #-0x0120] ; Vector from VicVectAddr
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IRQ_Handler B IRQ_Handler
FIQ_Handler B FIQ_Handler
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
; Clock Setup ------------------------------------------------------------------
IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0)
LDR R0, =SCB_BASE
MOV R1, #0xAA
MOV R2, #0x55
; Configure and Enable PLL
LDR R3, =SCS_Val ; Enable main oscillator
STR R3, [R0, #SCS_OFS]
IF (SCS_Val:AND:OSCEN) != 0
OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize
ANDS R3, R3, #OSCSTAT
BEQ OSC_Loop
ENDIF
LDR R3, =CLKSRCSEL_Val ; Select PLL source clock
STR R3, [R0, #CLKSRCSEL_OFS]
LDR R3, =PLLCFG_Val
STR R3, [R0, #PLLCFG_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
MOV R3, #PLLCON_PLLE
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
IF (CLKSRCSEL_Val:AND:3) != 2
; Wait until PLL Locked (if source is not RTC oscillator)
PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
ANDS R3, R3, #PLLSTAT_PLOCK
BEQ PLL_Loop
ELSE
; Wait at least 200 cycles (if source is RTC oscillator)
MOV R3, #(200/4)
PLL_Loop SUBS R3, R3, #1
BNE PLL_Loop
ENDIF
M_N_Lock LDR R3, [R0, #PLLSTAT_OFS]
LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N)
AND R3, R3, R4
LDR R4, =PLLCFG_Val
EORS R3, R3, R4
BNE M_N_Lock
; Setup CPU clock divider
MOV R3, #CCLKCFG_Val
STR R3, [R0, #CCLKCFG_OFS]
; Setup USB clock divider
LDR R3, =USBCLKCFG_Val
STR R3, [R0, #USBCLKCFG_OFS]
; Setup Peripheral Clock
LDR R3, =PCLKSEL0_Val
STR R3, [R0, #PCLKSEL0_OFS]
LDR R3, =PCLKSEL1_Val
STR R3, [R0, #PCLKSEL1_OFS]
; Switch to PLL Clock
MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
ENDIF ; CLOCK_SETUP
; Setup Memory Accelerator Module ----------------------------------------------
IF MAM_SETUP != 0
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val
STR R1, [R0, #MAMTIM_OFS]
MOV R1, #MAMCR_Val
STR R1, [R0, #MAMCR_OFS]
ENDIF ; MAM_SETUP
; Setup External Memory Controller ---------------------------------------------
IF (:DEF:SETUP_EMC):LOR:(EMC_SETUP != 0)
LDR R0, =EMC_BASE
LDR R1, =SCB_BASE
LDR R2, =PCB_BASE
LDR R4, =EMC_PCONP_Const ; Enable EMC
LDR R3, [R1, #PCONP_OFS]
ORR R4, R4, R3
STR R4, [R1, #PCONP_OFS]
LDR R4, =EMC_CTRL_Val
STR R4, [R0, #EMC_CTRL_OFS]
LDR R4, =EMC_CONFIG_Val
STR R4, [R0, #EMC_CONFIG_OFS]
; Setup pin functions for External Bus functionality
LDR R4, =EMC_PINSEL5_Val
STR R4, [R2, #PINSEL5_OFS]
LDR R4, =EMC_PINSEL6_Val
STR R4, [R2, #PINSEL6_OFS]
LDR R4, =EMC_PINSEL8_Val
STR R4, [R2, #PINSEL8_OFS]
LDR R4, =EMC_PINSEL9_Val
STR R4, [R2, #PINSEL9_OFS]
; Setup Dynamic Memory Interface
IF (EMC_DYNAMIC_SETUP != 0)
LDR R4, =EMC_DYN_RP_Val
STR R4, [R0, #EMC_DYN_RP_OFS]
LDR R4, =EMC_DYN_RAS_Val
STR R4, [R0, #EMC_DYN_RAS_OFS]
LDR R4, =EMC_DYN_SREX_Val
STR R4, [R0, #EMC_DYN_SREX_OFS]
LDR R4, =EMC_DYN_APR_Val
STR R4, [R0, #EMC_DYN_APR_OFS]
LDR R4, =EMC_DYN_DAL_Val
STR R4, [R0, #EMC_DYN_DAL_OFS]
LDR R4, =EMC_DYN_WR_Val
STR R4, [R0, #EMC_DYN_WR_OFS]
LDR R4, =EMC_DYN_RC_Val
STR R4, [R0, #EMC_DYN_RC_OFS]
LDR R4, =EMC_DYN_RFC_Val
STR R4, [R0, #EMC_DYN_RFC_OFS]
LDR R4, =EMC_DYN_XSR_Val
STR R4, [R0, #EMC_DYN_XSR_OFS]
LDR R4, =EMC_DYN_RRD_Val
STR R4, [R0, #EMC_DYN_RRD_OFS]
LDR R4, =EMC_DYN_MRD_Val
STR R4, [R0, #EMC_DYN_MRD_OFS]
LDR R4, =EMC_DYN_RD_CFG_Val
STR R4, [R0, #EMC_DYN_RD_CFG_OFS]
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