📄 zgemm_kernel_cell.s
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/*********************************************************************//* *//* Optimized BLAS libraries *//* By Kazushige Goto <kgoto@tacc.utexas.edu> *//* *//* Copyright (c) The University of Texas, 2005. All rights reserved. *//* UNIVERSITY EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES CONCERNING *//* THIS SOFTWARE AND DOCUMENTATION, INCLUDING ANY WARRANTIES OF *//* MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, *//* NON-INFRINGEMENT AND WARRANTIES OF PERFORMANCE, AND ANY WARRANTY *//* THAT MIGHT OTHERWISE ARISE FROM COURSE OF DEALING OR USAGE OF *//* TRADE. NO WARRANTY IS EITHER EXPRESS OR IMPLIED WITH RESPECT TO *//* THE USE OF THE SOFTWARE OR DOCUMENTATION. *//* Under no circumstances shall University be liable for incidental, *//* special, indirect, direct or consequential damages or loss of *//* profits, interruption of business, or related expenses which may *//* arise from use of Software or Documentation, including but not *//* limited to those resulting from defects in Software and/or *//* Documentation, or loss or inaccuracy of data of any kind. *//*********************************************************************/#define ASSEMBLER#include "common.h" #ifndef __64BIT__#define LOAD lwz#else#define LOAD ld#endif#ifdef __64BIT__#define STACKSIZE 320#define ALPHA_R 296(SP)#define ALPHA_I 304(SP)#define FZERO 312(SP)#else#define STACKSIZE 256#define ALPHA_R 224(SP)#define ALPHA_I 232(SP)#define FZERO 240(SP)#endif#define M r3#define N r4#define K r5#ifdef linux#ifndef __64BIT__#define A r6#define B r7#define C r8#define LDC r9#define OFFSET r10#else#define A r8#define B r9#define C r10#define LDC r6#define OFFSET r7#endif#endif#if defined(_AIX) || defined(__APPLE__)#if !defined(__64BIT__) && defined(DOUBLE)#define A r10#define B r6#define C r7#define LDC r8#define OFFSET r9#else#define A r8#define B r9#define C r10#define LDC r6#define OFFSET r7#endif#endif#define TEMP r22#define KK r23#define I r24#define J r25#define AO r26#define BO r27#define CO1 r28#define CO2 r29#define PREA r30#define PREC r31#define PREB PREA #ifndef NEEDPARAM#ifndef DOUBLE#include "../cparam.h"#else#include "../zparam.h"#endif PROLOGUE PROFCODE addi SP, SP, -STACKSIZE li r0, 0 stfd f14, 0(SP) stfd f15, 8(SP) stfd f16, 16(SP) stfd f17, 24(SP) stfd f18, 32(SP) stfd f19, 40(SP) stfd f20, 48(SP) stfd f21, 56(SP) stfd f22, 64(SP) stfd f23, 72(SP) stfd f24, 80(SP) stfd f25, 88(SP) stfd f26, 96(SP) stfd f27, 104(SP) stfd f28, 112(SP) stfd f29, 120(SP) stfd f30, 128(SP) stfd f31, 136(SP)#ifdef __64BIT__ std r31, 144(SP) std r30, 152(SP) std r29, 160(SP) std r28, 168(SP) std r27, 176(SP) std r26, 184(SP) std r25, 192(SP) std r24, 200(SP)#ifdef TRMMKERNEL std r23, 208(SP) std r22, 216(SP)#endif#else stw r31, 144(SP) stw r30, 148(SP) stw r29, 152(SP) stw r28, 156(SP) stw r27, 160(SP) stw r26, 164(SP) stw r25, 168(SP) stw r24, 172(SP)#ifdef TRMMKERNEL stw r23, 176(SP) stw r22, 180(SP)#endif#endif stfd f1, ALPHA_R stfd f2, ALPHA_I stw r0, FZERO#ifdef linux#ifdef __64BIT__ ld LDC, 112 + STACKSIZE(SP)#endif#endif#if defined(_AIX) || defined(__APPLE__)#ifdef __64BIT__ ld LDC, 112 + STACKSIZE(SP)#else#ifdef DOUBLE lwz B, 56 + STACKSIZE(SP) lwz C, 60 + STACKSIZE(SP) lwz LDC, 64 + STACKSIZE(SP)#else lwz LDC, 56 + STACKSIZE(SP)#endif#endif#endif#ifdef TRMMKERNEL#if defined(linux) && defined(__64BIT__) ld OFFSET, 120 + STACKSIZE(SP)#endif#if defined(_AIX) || defined(__APPLE__)#ifdef __64BIT__ ld OFFSET, 120 + STACKSIZE(SP)#else#ifdef DOUBLE lwz OFFSET, 68 + STACKSIZE(SP)#else lwz OFFSET, 60 + STACKSIZE(SP)#endif#endif#endif#if defined(TRMMKERNEL) && !defined(LEFT) neg KK, OFFSET#endif#endif slwi LDC, LDC, ZBASE_SHIFT cmpwi cr0, M, 0 ble LL(999) cmpwi cr0, N, 0 ble LL(999) cmpwi cr0, K, 0 ble LL(999)#ifndef PREFETCHTEST li PREC, 3 * SIZE li PREA, 16 * 12 * SIZE#else#ifdef linux#ifndef __64BIT__ lwz PREA, 16 + STACKSIZE(SP) lwz PREC, 20 + STACKSIZE(SP)#else ld PREA, 136 + STACKSIZE(SP) ld PREC, 144 + STACKSIZE(SP)#endif#endif#if defined(_AIX) || defined(__APPLE__)#ifdef __64BIT__ ld PREA, 136 + STACKSIZE(SP) ld PREC, 144 + STACKSIZE(SP)#else#ifdef DOUBLE lwz PREA, 72 + STACKSIZE(SP) lwz PREC, 76 + STACKSIZE(SP)#else lwz PREA, 68 + STACKSIZE(SP) lwz PREC, 72 + STACKSIZE(SP)#endif#endif#endif#endif lfs f0, FZERO srawi. J, N, 1 ble LL(30) .align 4LL(10): fmr f1, f0 fmr f2, f0 fmr f3, f0 fmr f4, f0 fmr f5, f0 fmr f6, f0 fmr f7, f0 fmr f8, f0 fmr f9, f0 fmr f10, f0 fmr f11, f0 fmr f12, f0 fmr f13, f0 fmr f14, f0 fmr f15, f0 mr CO1, C add CO2, C, LDC add C, CO2, LDC#if defined(TRMMKERNEL) && defined(LEFT) mr KK, OFFSET#endif srawi. I, M, 1 mr AO, A ble LL(20) .align 4LL(11):#ifndef TRMMKERNEL LFD f16, 0 * SIZE(AO) LFD f17, 1 * SIZE(AO) LFD f18, 2 * SIZE(AO) LFD f19, 3 * SIZE(AO) LFD f20, 0 * SIZE(B) LFD f21, 1 * SIZE(B) LFD f22, 2 * SIZE(B) LFD f23, 3 * SIZE(B) LFD f24, 4 * SIZE(AO) LFD f25, 5 * SIZE(AO) LFD f26, 6 * SIZE(AO) LFD f28, 4 * SIZE(B) LFD f29, 5 * SIZE(B) LFD f30, 6 * SIZE(B) PREFETCH_C1 nop nop PREFETCH_C2 srawi. r0, K, 2 mr BO, B mtspr CTR, r0 ble LL(15)#else#if (defined(TRMMKERNEL) && defined(LEFT) && defined(TRANSA)) || \ (defined(TRMMKERNEL) && !defined(LEFT) && !defined(TRANSA)) LFD f16, 0 * SIZE(AO) LFD f17, 1 * SIZE(AO) LFD f18, 2 * SIZE(AO) LFD f19, 3 * SIZE(AO) LFD f20, 0 * SIZE(B) LFD f21, 1 * SIZE(B) LFD f22, 2 * SIZE(B) LFD f23, 3 * SIZE(B) LFD f24, 4 * SIZE(AO) LFD f25, 5 * SIZE(AO) LFD f26, 6 * SIZE(AO) LFD f28, 4 * SIZE(B) LFD f29, 5 * SIZE(B) LFD f30, 6 * SIZE(B) mr BO, B#else slwi r0, KK, 1 + ZBASE_SHIFT add AO, AO, r0 add BO, B, r0 LFD f16, 0 * SIZE(AO) LFD f17, 1 * SIZE(AO) LFD f18, 2 * SIZE(AO) LFD f19, 3 * SIZE(AO) LFD f20, 0 * SIZE(BO) LFD f21, 1 * SIZE(BO) LFD f22, 2 * SIZE(BO) LFD f23, 3 * SIZE(BO) LFD f24, 4 * SIZE(AO) LFD f25, 5 * SIZE(AO) LFD f26, 6 * SIZE(AO) LFD f28, 4 * SIZE(BO) LFD f29, 5 * SIZE(BO) LFD f30, 6 * SIZE(BO)#endif PREFETCH_C1 PREFETCH_C2#if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA)) sub TEMP, K, KK#elif defined(LEFT) addi TEMP, KK, 2#else addi TEMP, KK, 2#endif srawi. TEMP, TEMP, 2 mtspr CTR, TEMP ble LL(15)#endif .align 4#define NOP1 mr r18, r18#define NOP2 mr r19, r19LL(12): FMADD f0, f16, f20, f0 dcbt AO, PREA FMADD f4, f16, f21, f4 dcbt BO, PREB FMADD f8, f16, f22, f8 LFD f31, 7 * SIZE(BO) FMADD f12, f16, f23, f12 LFD f27, 7 * SIZE(AO) FMADD f1, f17, f20, f1 LFD f16, 8 * SIZE(AO) FMADD f5, f17, f21, f5 NOP2 FMADD f9, f17, f22, f9 NOP1 FMADD f13, f17, f23, f13 LFD f17, 9 * SIZE(AO) FMADD f2, f18, f20, f2 NOP1 FMADD f6, f18, f21, f6 NOP2 FMADD f10, f18, f22, f10 NOP1 FMADD f14, f18, f23, f14 LFD f18, 10 * SIZE(AO) FMADD f3, f19, f20, f3 LFD f20, 8 * SIZE(BO) FMADD f7, f19, f21, f7 LFD f21, 9 * SIZE(BO) FMADD f11, f19, f22, f11 LFD f22, 10 * SIZE(BO) FMADD f15, f19, f23, f15 LFD f19, 11 * SIZE(AO) FMADD f0, f24, f28, f0 LFD f23, 11 * SIZE(BO) FMADD f4, f24, f29, f4 NOP2 FMADD f8, f24, f30, f8 NOP1 FMADD f12, f24, f31, f12 LFD f24, 12 * SIZE(AO) FMADD f1, f25, f28, f1 NOP1 FMADD f5, f25, f29, f5 NOP2 FMADD f9, f25, f30, f9 NOP1 FMADD f13, f25, f31, f13 LFD f25, 13 * SIZE(AO) FMADD f2, f26, f28, f2 NOP1 FMADD f6, f26, f29, f6 NOP2 FMADD f10, f26, f30, f10 NOP1 FMADD f14, f26, f31, f14 LFD f26, 14 * SIZE(AO) FMADD f3, f27, f28, f3 LFD f28, 12 * SIZE(BO) FMADD f7, f27, f29, f7 LFD f29, 13 * SIZE(BO) FMADD f11, f27, f30, f11 LFD f30, 14 * SIZE(BO) FMADD f15, f27, f31, f15 LFD f27, 15 * SIZE(AO) FMADD f0, f16, f20, f0 LFD f31, 15 * SIZE(BO) FMADD f4, f16, f21, f4 NOP2 FMADD f8, f16, f22, f8 NOP1 FMADD f12, f16, f23, f12 LFD f16, 16 * SIZE(AO) FMADD f1, f17, f20, f1 NOP1 FMADD f5, f17, f21, f5 NOP2 FMADD f9, f17, f22, f9 NOP1 FMADD f13, f17, f23, f13 LFD f17, 17 * SIZE(AO) FMADD f2, f18, f20, f2 NOP1 FMADD f6, f18, f21, f6 NOP2 FMADD f10, f18, f22, f10 NOP1 FMADD f14, f18, f23, f14 LFD f18, 18 * SIZE(AO) FMADD f3, f19, f20, f3 LFD f20, 16 * SIZE(BO) FMADD f7, f19, f21, f7 LFD f21, 17 * SIZE(BO) FMADD f11, f19, f22, f11 LFD f22, 18 * SIZE(BO) FMADD f15, f19, f23, f15 LFD f19, 19 * SIZE(AO) FMADD f0, f24, f28, f0 LFD f23, 19 * SIZE(BO) FMADD f4, f24, f29, f4 NOP2 FMADD f8, f24, f30, f8 NOP1 FMADD f12, f24, f31, f12 LFD f24, 20 * SIZE(AO) FMADD f1, f25, f28, f1 NOP1 FMADD f5, f25, f29, f5 NOP2 FMADD f9, f25, f30, f9 NOP1 FMADD f13, f25, f31, f13 LFD f25, 21 * SIZE(AO) FMADD f2, f26, f28, f2 NOP1 FMADD f6, f26, f29, f6 NOP2 FMADD f10, f26, f30, f10 NOP1 FMADD f14, f26, f31, f14 LFD f26, 22 * SIZE(AO) FMADD f3, f27, f28, f3 LFD f28, 20 * SIZE(BO) FMADD f7, f27, f29, f7 LFD f29, 21 * SIZE(BO) FMADD f11, f27, f30, f11 LFD f30, 22 * SIZE(BO) FMADD f15, f27, f31, f15 addi AO, AO, 16 * SIZE addi BO, BO, 16 * SIZE bdnz LL(12) .align 4LL(15):#ifndef TRMMKERNEL andi. r0, K, 3 lfd f30, ALPHA_R lfd f31, ALPHA_I mtspr CTR, r0 ble LL(KERNEL_MainFinish)#else#if (defined(LEFT) && !defined(TRANSA)) || (!defined(LEFT) && defined(TRANSA)) sub TEMP, K, KK#elif defined(LEFT) addi TEMP, KK, 2#else addi TEMP, KK, 2#endif andi. TEMP, TEMP, 3 lfd f30, ALPHA_R lfd f31, ALPHA_I mtspr CTR, TEMP ble LL(KERNEL_MainFinish)#endif .align 4LL(16): FMADD f0, f16, f20, f0 FMADD f5, f17, f21, f5 FMADD f10, f18, f22, f10 FMADD f15, f19, f23, f15 FMADD f1, f17, f20, f1 FMADD f2, f18, f20, f2 FMADD f3, f19, f20, f3 FMADD f4, f16, f21, f4 FMADD f6, f18, f21, f6 FMADD f7, f19, f21, f7 FMADD f8, f16, f22, f8 FMADD f9, f17, f22, f9 FMADD f11, f19, f22, f11 FMADD f12, f16, f23, f12 FMADD f13, f17, f23, f13 FMADD f14, f18, f23, f14 LFD f16, 4 * SIZE(AO) LFD f17, 5 * SIZE(AO) LFD f18, 6 * SIZE(AO) LFD f19, 7 * SIZE(AO) LFD f20, 4 * SIZE(BO) LFD f21, 5 * SIZE(BO) LFD f22, 6 * SIZE(BO) LFD f23, 7 * SIZE(BO) addi BO, BO, 4 * SIZE addi AO, AO, 4 * SIZE bdnz LL(16) .align 4LL(KERNEL_MainFinish):#ifndef TRMMKERNEL LFD f16, 0 * SIZE(CO1) LFD f17, 1 * SIZE(CO1) LFD f18, 2 * SIZE(CO1) LFD f19, 3 * SIZE(CO1)#endif
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