📄 ztrsm_kernel_rt.s

📁 Optimized GotoBLAS libraries
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	prefetch [AO + APREFETCHSIZE * SIZE], 0	FADD3	c02, t2, c02	add	BO,  8 * SIZE, BO	FMUL	a1, b2, t2	LDF	[AO + 4 * SIZE], a1	FADD2	c03, t3, c03	cmp	L, 0	FMUL	a2, b1, t3	LDF	[BO - 4 * SIZE], b1	FADD4	c04, t4, c04	nop	FMUL	a2, b2, t4	LDF	[AO + 5 * SIZE], a2	FADD1	c01, t1, c01	nop	FMUL	a3, b3, t1	LDF	[BO - 3 * SIZE], b2	FADD3	c02, t2, c02	nop	FMUL	a3, b4, t2	LDF	[AO + 6 * SIZE], a3	FADD2	c03, t3, c03	nop	FMUL	a4, b3, t3	LDF	[BO - 2 * SIZE], b3	FADD4	c04, t4, c04	nop	FMUL	a4, b4, t4	LDF	[AO + 7 * SIZE], a4	FADD1	c01, t1, c01	nop	FMUL	a1, b1, t1	LDF	[BO - 1 * SIZE], b4	FADD3	c02, t2, c02	FMUL	a1, b2, t2	LDF	[AO +  8 * SIZE], a1	FADD2	c03, t3, c03	FMUL	a2, b1, t3	LDF	[BO +  0 * SIZE], b1	FADD4	c04, t4, c04	FMUL	a2, b2, t4	LDF	[AO +  9 * SIZE], a2	FADD1	c01, t1, c01	FMUL	a3, b3, t1	LDF	[BO +  1 * SIZE], b2	FADD3	c02, t2, c02	FMUL	a3, b4, t2	LDF	[AO + 10 * SIZE], a3	FADD2	c03, t3, c03	FMUL	a4, b3, t3	LDF	[BO +  2 * SIZE], b3	FADD4	c04, t4, c04	FMUL	a4, b4, t4	LDF	[AO + 11 * SIZE], a4	add	AO,  8 * SIZE, AO	bg,pt	%icc, .LL152	LDF	[BO +  3 * SIZE], b4.LL155:#if defined(LT) || defined(RN)	and	KK,  3, L#else	and	TEMP1, 3, L#endif	cmp	L,  0	ble,a,pn %icc, .LL159	nop.LL156:	FADD1	c01, t1, c01	add	AO, 2 * SIZE, AO	FMUL	a1, b1, t1	add	BO, 2 * SIZE, BO	FADD3	c02, t2, c02	add	L, -1, L	FMUL	a1, b2, t2	LDF	[AO + 0 * SIZE], a1	FADD2	c03, t3, c03	FMUL	a2, b1, t3	LDF	[BO + 0 * SIZE], b1	cmp	L, 0	FADD4	c04, t4, c04	FMUL	a2, b2, t4	LDF	[BO + 1 * SIZE], b2	bg,pt	%icc, .LL156	LDF	[AO + 1 * SIZE], a2.LL159:	FADD1	c01, t1, c01	FADD3	c02, t2, c02	FADD2	c03, t3, c03	FADD4	c04, t4, c04	FADD	c01, c04, c01	FADD	c02, c03, c02#if defined(LN) || defined(RT)	sub	KK, 1, TEMP1	sll	TEMP1, 0 + ZBASE_SHIFT, TEMP1	add	AORIG, TEMP1, AO	add	B,     TEMP1, BO#endif#if defined(LN) || defined(LT)	LDF	[BO +  0 * SIZE], a1	LDF	[BO +  1 * SIZE], a2	FSUB	a1, c01, c01	FSUB	a2, c02, c02#else	LDF	[AO +  0 * SIZE], a1	LDF	[AO +  1 * SIZE], a2	FSUB	a1, c01, c01	FSUB	a2, c02, c02#endif#ifdef LN	LDF	[AO +  0 * SIZE], a1	LDF	[AO +  1 * SIZE], a2	FMUL	a1, c01, t1	FMUL	a2, c02, t2	FMUL	a1, c02, t3	FMUL	a2, c01, t4	FADD4	t1, t2, c01	FADD2	t3, t4, c02#endif#ifdef LT	LDF	[AO +  0 * SIZE], a1	LDF	[AO +  1 * SIZE], a2	FMUL	a1, c01, t1	FMUL	a2, c02, t2	FMUL	a1, c02, t3	FMUL	a2, c01, t4	FADD4	t1, t2, c01	FADD2	t3, t4, c02#endif#ifdef RN	LDF	[BO +  0 * SIZE], a1	LDF	[BO +  1 * SIZE], a2	FMUL	a1, c01, t1	FMUL	a2, c02, t2	FMUL	a1, c02, t3	FMUL	a2, c01, t4	FADD4	t1, t2, c01	FADD3	t3, t4, c02#endif#ifdef RT	LDF	[BO +  0 * SIZE], a1	LDF	[BO +  1 * SIZE], a2	FMUL	a1, c01, t1	FMUL	a2, c02, t2	FMUL	a1, c02, t3	FMUL	a2, c01, t4	FADD4	t1, t2, c01	FADD3	t3, t4, c02#endif#ifdef LN	add	C1, -2 * SIZE, C1#endif#if defined(LN) || defined(LT)	STF	c01, [BO +  0 * SIZE]	STF	c02, [BO +  1 * SIZE]#else	STF	c01, [AO +  0 * SIZE]	STF	c02, [AO +  1 * SIZE]#endif	STF	c01, [C1 + 0 * SIZE]	STF	c02, [C1 + 1 * SIZE]	FMOV	FZERO, t1	FMOV	FZERO, t2	FMOV	FZERO, t3	FMOV	FZERO, t4#ifndef LN	add	C1, 2 * SIZE, C1#endif#ifdef RT	sll	K, 0 + ZBASE_SHIFT, TEMP1	add	AORIG, TEMP1, AORIG#endif#if defined(LT) || defined(RN)	sub	K, KK, TEMP1	sll	TEMP1, 0 + ZBASE_SHIFT, TEMP1	add	AO, TEMP1, AO	add	BO, TEMP1, BO#endif#ifdef LT	add	KK, 1, KK#endif#ifdef LN	sub	KK, 1, KK#endif.LL199:#ifdef LN	sll	K, 0 + ZBASE_SHIFT, TEMP1	add	B, TEMP1, B#endif#if defined(LT) || defined(RN)	mov	BO, B#endif#ifdef RN	add	KK, 1, KK#endif#ifdef RT	sub	KK, 1, KK#endif.LL100:	sra	N, 1, J	cmp	J, 0	ble,pn	%icc, .LL999	nop.LL11:#ifdef RT	sll	K, 1 + ZBASE_SHIFT, TEMP1	sub	B, TEMP1, B	add	LDC, LDC, TEMP1	sub	C, TEMP1, C#endif	FMOV	FZERO, t1	FMOV	FZERO, t2	FMOV	FZERO, t3	sra	M, 1, I	mov	C, C1	add	C, LDC, C2#ifdef LN	add	M, OFFSET, KK#endif#ifdef LT	mov	OFFSET, KK#endif#if defined(LN) || defined(RT)	mov	A, AORIG#else	mov	A, AO#endif	cmp	I, 0#ifndef RT	add	C2, LDC, C#endif	ble,pn	%icc, .LL50	FMOV	FZERO, t4.LL21:#if defined(LT) || defined(RN)	sra	KK, 2, L	mov	B, BO	cmp	L,  0#else#ifdef LN	sll	K,  1 + ZBASE_SHIFT, TEMP1	sub	AORIG, TEMP1, AORIG#endif	sll	KK, 1 + ZBASE_SHIFT, TEMP1	add	AORIG, TEMP1, AO	add	B,     TEMP1, BO	sub	K, KK, TEMP1	sra	TEMP1, 2, L	cmp	L,  0#endif	FMOV	FZERO, t1	FMOV	FZERO, t2	FMOV	FZERO, t3	FMOV	FZERO, t4	FMOV	FZERO, c01	FMOV	FZERO, c02	LDF	[AO + 0 * SIZE], a1	FMOV	FZERO, c03	LDF	[BO + 0 * SIZE], b1	FMOV	FZERO, c04	LDF	[AO + 1 * SIZE], a2	FMOV	FZERO, c05	LDF	[BO + 1 * SIZE], b2	FMOV	FZERO, c06	LDF	[AO + 2 * SIZE], a3	FMOV	FZERO, c07	LDF	[BO + 2 * SIZE], b3	FMOV	FZERO, c08	LDF	[AO + 3 * SIZE], a4	FMOV	FZERO, c09	LDF	[BO + 3 * SIZE], b4	FMOV	FZERO, c10	LDF	[BO +  4 * SIZE], b5	FMOV	FZERO, c11	LDF	[AO +  4 * SIZE], a5	FMOV	FZERO, c12	prefetch [C1 + 3 * SIZE], 3	FMOV	FZERO, c13	prefetch [C2 + 3 * SIZE], 3	FMOV	FZERO, c14	FMOV	FZERO, c15	ble,pn	%icc, .LL25	FMOV	FZERO, c16.LL22:	FADD2	c04, t1, c04	prefetch [AO + APREFETCHSIZE * SIZE], APREFETCH_CATEGORY	FMUL	a1, b1, t1	nop	FADD4	c08, t2, c08	prefetch [BO + BPREFETCHSIZE * SIZE], BPREFETCH_CATEGORY	FMUL	a1, b2, t2	add	AO, 16 * SIZE, AO	FADD2	c12, t3, c12	LDF	[AO - 13 * SIZE], a4	FMUL	a1, b3, t3	add	BO, 16 * SIZE, BO	FADD4	c16, t4, c16	nop	FMUL	a1, b4, t4	LDF	[AO -  8 * SIZE], a1	FADD1	c01, t1, c01	nop	FMUL	a2, b1, t1	nop	FADD3	c05, t2, c05	nop	FMUL	a2, b2, t2	nop	FADD1	c09, t3, c09	nop	FMUL	a2, b3, t3	nop	FADD3	c13, t4, c13	add	L, -1, L	FMUL	a2, b4, t4	LDF	[AO - 11 * SIZE], a2	FADD2	c02, t1, c02	nop	FMUL	a3, b1, t1	nop	FADD4	c06, t2, c06	nop	FMUL	a3, b2, t2	nop	FADD2	c10, t3, c10	nop	FMUL	a3, b3, t3	nop	FADD4	c14, t4, c14	nop	FMUL	a3, b4, t4	LDF	[AO - 10 * SIZE], a3	FADD1	c03, t1, c03	nop	FMUL	a4, b1, t1	LDF	[BO -  8 * SIZE], b1	FADD3	c07, t2, c07	nop	FMUL	a4, b2, t2	LDF	[BO - 11 * SIZE], b2	FADD1	c11, t3, c11	nop	FMUL	a4, b3, t3	LDF	[BO - 10 * SIZE], b3	FADD3	c15, t4, c15	nop	FMUL	a4, b4, t4	LDF	[BO -  9 * SIZE], b4	FADD2	c04, t1, c04	nop	FMUL	a5, b5, t1	LDF	[AO -  9 * SIZE], a4	FADD4	c08, t2, c08	nop	FMUL	a5, b2, t2	nop	FADD2	c12, t3, c12	nop	FMUL	a5, b3, t3	nop	FADD4	c16, t4, c16	nop	FMUL	a5, b4, t4	LDF	[AO - 4 * SIZE], a5	FADD1	c01, t1, c01	nop	FMUL	a2, b5, t1	nop	FADD3	c05, t2, c05	nop	FMUL	a2, b2, t2	nop	FADD1	c09, t3, c09	nop	FMUL	a2, b3, t3	nop	FADD3	c13, t4, c13	nop	FMUL	a2, b4, t4	LDF	[AO -  7 * SIZE], a2	FADD2	c02, t1, c02	nop	FMUL	a3, b5, t1	nop	FADD4	c06, t2, c06	nop	FMUL	a3, b2, t2	nop	FADD2	c10, t3, c10	nop	FMUL	a3, b3, t3	nop	FADD4	c14, t4, c14	nop	FMUL	a3, b4, t4	LDF	[AO -  6 * SIZE], a3	FADD1	c03, t1, c03	nop	FMUL	a4, b5, t1	LDF	[BO - 4 * SIZE], b5	FADD3	c07, t2, c07	nop	FMUL	a4, b2, t2	LDF	[BO -  7 * SIZE], b2	FADD1	c11, t3, c11	nop	FMUL	a4, b3, t3	LDF	[BO -  6 * SIZE], b3	FADD3	c15, t4, c15	nop	FMUL	a4, b4, t4	LDF	[BO -  5 * SIZE], b4	FADD2	c04, t1, c04	nop	FMUL	a1, b1, t1	LDF	[AO -  5 * SIZE], a4	FADD4	c08, t2, c08	nop	FMUL	a1, b2, t2	nop	FADD2	c12, t3, c12	nop	FMUL	a1, b3, t3	nop	FADD4	c16, t4, c16	nop	FMUL	a1, b4, t4	LDF	[AO -  0 * SIZE], a1	FADD1	c01, t1, c01	nop	FMUL	a2, b1, t1	nop#ifdef DOUBLE	prefetch [AO + (APREFETCHSIZE + 8) * SIZE], APREFETCH_CATEGORY#else	nop#endif	FADD3	c05, t2, c05	nop	FMUL	a2, b2, t2	FADD1	c09, t3, c09	nop	FMUL	a2, b3, t3	nop	FADD3	c13, t4, c13	nop	FMUL	a2, b4, t4	nop	FADD2	c02, t1, c02	nop	FMUL	a3, b1, t1	LDF	[AO - 3 * SIZE], a2	FADD4	c06, t2, c06#ifdef DOUBLE	prefetch [BO + (BPREFETCHSIZE + 8) * SIZE], BPREFETCH_CATEGORY#else	nop#endif	FMUL	a3, b2, t2	nop	FADD2	c10, t3, c10	nop	FMUL	a3, b3, t3	nop	FADD4	c14, t4, c14	nop	FMUL	a3, b4, t4	LDF	[AO - 2 * SIZE], a3	FADD1	c03, t1, c03	nop	FMUL	a4, b1, t1	LDF	[BO -  0 * SIZE], b1	FADD3	c07, t2, c07	nop	FMUL	a4, b2, t2	LDF	[BO - 3 * SIZE], b2	FADD1	c11, t3, c11	nop	FMUL	a4, b3, t3	LDF	[BO - 2 * SIZE], b3	FADD3	c15, t4, c15	nop	FMUL	a4, b4, t4	LDF	[BO - 1 * SIZE], b4	FADD2	c04, t1, c04	nop	FMUL	a5, b5, t1	LDF	[AO - 1 * SIZE], a4	FADD4	c08, t2, c08	FMUL	a5, b2, t2	FADD2	c12, t3, c12	FMUL	a5, b3, t3	FADD4	c16, t4, c16	nop	FMUL	a5, b4, t4	LDF	[AO +  4 * SIZE], a5	FADD1	c01, t1, c01	nop	FMUL	a2, b5, t1	nop	FADD3	c05, t2, c05	nop	FMUL	a2, b2, t2	nop	FADD1	c09, t3, c09	nop	FMUL	a2, b3, t3	nop	FADD3	c13, t4, c13	nop	FMUL	a2, b4, t4	LDF	[AO +  1 * SIZE], a2	FADD2	c02, t1, c02	nop	FMUL	a3, b5, t1	nop	FADD4	c06, t2, c06	nop	FMUL	a3, b2, t2	nop	FADD2	c10, t3, c10	nop	FMUL	a3, b3, t3	nop	FADD4	c14, t4, c14	nop	FMUL	a3, b4, t4	LDF	[AO +  2 * SIZE], a3	FADD1	c03, t1, c03	cmp	L, 0	FMUL	a4, b5, t1	LDF	[BO +  4 * SIZE], b5	FADD3	c07, t2, c07	nop	FMUL	a4, b2, t2	LDF	[BO +  1 * SIZE], b2	FADD1	c11, t3, c11	nop	FMUL	a4, b3, t3	LDF	[BO +  2 * SIZE], b3	FADD3	c15, t4, c15	FMUL	a4, b4, t4	bg,pt	%icc, .LL22	LDF	[BO +  3 * SIZE], b4.LL25:#if defined(LT) || defined(RN)	and	KK,  3, L#else	and	TEMP1, 3, L#endif	cmp	L,  0	ble,pn %icc, .LL29	nop	.LL26:	FADD2	c04, t1, c04	LDF	[AO +  3 * SIZE], a4	FMUL	a1, b1, t1	add	AO, 4 * SIZE, AO	FADD4	c08, t2, c08	add	BO, 4 * SIZE, BO	FMUL	a1, b2, t2	add	L, -1, L	FADD2	c12, t3, c12	nop	FMUL	a1, b3, t3	cmp	L, 0	FADD4	c16, t4, c16	nop	FMUL	a1, b4, t4	LDF	[AO + 0 * SIZE], a1	FADD1	c01, t1, c01	nop	FMUL	a2, b1, t1	nop	FADD3	c05, t2, c05	nop	FMUL	a2, b2, t2	nop	FADD1	c09, t3, c09	nop	FMUL	a2, b3, t3	nop	FADD3	c13, t4, c13	nop	FMUL	a2, b4, t4	LDF	[AO + 1 * SIZE], a2	FADD2	c02, t1, c02	nop	FMUL	a3, b1, t1	nop	FADD4	c06, t2, c06	nop	FMUL	a3, b2, t2	nop	FADD2	c10, t3, c10	nop	FMUL	a3, b3, t3	nop	FADD4	c14, t4, c14	nop	FMUL	a3, b4, t4	LDF	[AO + 2 * SIZE], a3	FADD1	c03, t1, c03	nop	FMUL	a4, b1, t1	LDF	[BO + 0 * SIZE], b1	FADD3	c07, t2, c07	nop	FMUL	a4, b2, t2	LDF	[BO + 1 * SIZE], b2	FADD1	c11, t3, c11	nop	FMUL	a4, b3, t3	LDF	[BO + 2 * SIZE], b3	FADD3	c15, t4, c15	FMUL	a4, b4, t4	bg,pt	%icc, .LL26	LDF	[BO + 3 * SIZE], b4.LL29:#if defined(LN) || defined(RT)	sub	KK, 2, TEMP1	sll	TEMP1, 1 + ZBASE_SHIFT, TEMP1	add	AORIG, TEMP1, AO	add	B,     TEMP1, BO#endif	FADD2	c04, t1, c04	FADD4	c08, t2, c08	FADD2	c12, t3, c12	FADD4	c16, t4, c16	FADD	c01, c06, c01	FADD	c02, c05, c02	FADD	c03, c08, c03	FADD	c04, c07, c04	FADD	c09, c14, c09	FADD	c10, c13, c10	FADD	c11, c16, c11	FADD	c12, c15, c12#if defined(LN) || defined(LT)
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