trsm_kernel_cell_lt.s

Optimized GotoBLAS libraries

/*********************************************************************/
/*                                                                   */
/*             Optimized BLAS libraries                              */
/*                     By Kazushige Goto <[e-mail]>     */
/*                                                                   */
/* Copyright (c) The University of Texas, 2005. All rights reserved. */
/* UNIVERSITY EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES CONCERNING  */
/* THIS SOFTWARE AND DOCUMENTATION, INCLUDING ANY WARRANTIES OF      */
/* MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE,              */
/* NON-INFRINGEMENT AND WARRANTIES OF PERFORMANCE, AND ANY WARRANTY  */
/* THAT MIGHT OTHERWISE ARISE FROM COURSE OF DEALING OR USAGE OF     */
/* TRADE. NO WARRANTY IS EITHER EXPRESS OR IMPLIED WITH RESPECT TO   */
/* THE USE OF THE SOFTWARE OR DOCUMENTATION.                         */
/* Under no circumstances shall University be liable for incidental, */
/* special, indirect, direct or consequential damages or loss of     */
/* profits, interruption of business, or related expenses which may  */
/* arise from use of Software or Documentation, including but not    */
/* limited to those resulting from defects in Software and/or        */
/* Documentation, or loss or inaccuracy of data of any kind.         */
/*********************************************************************/

#define ASSEMBLER
#include "common.h"
		
#ifndef __64BIT__
#define LOAD	lwz
#else
#define LOAD	ld
#endif

#ifdef __64BIT__
#define STACKSIZE 320
#define ALPHA   296(SP)
#define FZERO	304(SP)
#else
#define STACKSIZE 240
#define ALPHA   224(SP)
#define FZERO	232(SP)
#endif

#define	M	r3
#define	N	r4
#define	K	r5

#ifdef linux
#ifndef __64BIT__
#define A	r6
#define	B	r7
#define	C	r8
#define	LDC	r9
#define OFFSET	r10
#else
#define A	r7
#define	B	r8
#define	C	r9
#define	LDC	r10
#define OFFSET	r6
#endif
#endif

#if defined(_AIX) || defined(__APPLE__)
#if !defined(__64BIT__) && defined(DOUBLE)
#define A	r8
#define	B	r9
#define	C	r10
#define	LDC	r7
#define OFFSET	r6
#else
#define A	r7
#define	B	r8
#define	C	r9
#define	LDC	r10
#define OFFSET	r6
#endif
#endif

#define AORIG	r18
#define TEMP	r19
#define KK	r20
#define	I	r21
#define J	r22
#define AO	r23
#define	BO	r24
#define	CO1	r25
#define CO2	r26
#define	CO3	r27
#define	CO4	r28

#define PREA	r29
#define PREB	r30
#define PREC	r31

#ifndef NEEDPARAM

#ifndef DOUBLE
#include "sparam.h"
#else
#include "dparam.h"
#endif

	PROLOGUE
	PROFCODE

	addi	SP, SP, -STACKSIZE
	li	r0, 0

	stfd	f14,    0(SP)
	stfd	f15,    8(SP)
	stfd	f16,   16(SP)
	stfd	f17,   24(SP)

	stfd	f18,   32(SP)
	stfd	f19,   40(SP)
	stfd	f20,   48(SP)
	stfd	f21,   56(SP)

	stfd	f22,   64(SP)
	stfd	f23,   72(SP)
	stfd	f24,   80(SP)
	stfd	f25,   88(SP)

	stfd	f26,   96(SP)
	stfd	f27,  104(SP)
	stfd	f28,  112(SP)
	stfd	f29,  120(SP)

	stfd	f30,  128(SP)
	stfd	f31,  136(SP)

#ifdef __64BIT__
	std	r31,  144(SP)
	std	r30,  152(SP)
	std	r29,  160(SP)
	std	r28,  168(SP)
	std	r27,  176(SP)
	std	r26,  184(SP)
	std	r25,  192(SP)
	std	r24,  200(SP)
	std	r23,  208(SP)
	std	r22,  216(SP)
	std	r21,  224(SP)
	std	r20,  232(SP)
	std	r19,  240(SP)
	std	r18,  248(SP)
#else
	stw	r31,  144(SP)
	stw	r30,  148(SP)
	stw	r29,  152(SP)
	stw	r28,  156(SP)
	stw	r27,  160(SP)
	stw	r26,  164(SP)
	stw	r25,  168(SP)
	stw	r24,  172(SP)
	stw	r23,  176(SP)
	stw	r22,  180(SP)
	stw	r21,  184(SP)
	stw	r20,  188(SP)
	stw	r19,  192(SP)
	stw	r18,  196(SP)
#endif

	stw	r0,  FZERO

#if defined(_AIX) || defined(__APPLE__)
#if !defined(__64BIT__) && defined(DOUBLE)
	lwz	LDC,    56 + STACKSIZE(SP)
#endif
#endif

	slwi	LDC, LDC, BASE_SHIFT

#if defined(linux) && defined(__64BIT__)
	ld	OFFSET,   112 + STACKSIZE(SP)
#endif

#if defined(_AIX) || defined(__APPLE__)
#ifdef __64BIT__
	ld	OFFSET,  112 + STACKSIZE(SP)
#else
#ifdef DOUBLE
	lwz	OFFSET,   60 + STACKSIZE(SP)
#else
	lwz	OFFSET,   56 + STACKSIZE(SP)
#endif
#endif
#endif

#ifdef LN
	mullw	r0, M, K
	slwi	r0, r0, BASE_SHIFT
	add	A, A, r0

	slwi	r0, M, BASE_SHIFT
	add	C, C, r0
#endif

#ifdef RN
	neg	KK, OFFSET
#endif

#ifdef RT
	mullw	r0, N, K
	slwi	r0, r0, BASE_SHIFT
	add	B, B, r0

	mullw	r0, N, LDC
	add	C, C, r0

	sub	KK, N, OFFSET
#endif

	cmpwi	cr0, M, 0
	ble	LL(999)
	cmpwi	cr0, N, 0
	ble	LL(999)
	cmpwi	cr0, K, 0
	ble	LL(999)

#ifndef PREFETCHTEST
#if defined(TRSMKERNEL) && defined(LN)
/* Direction is special */
#ifdef PPC970
	li	PREC,  -4 * SIZE
#endif
#ifdef POWER4
	li	PREC,  -4 * SIZE
#endif
#ifdef POWER5
	li	PREC,  -4 * SIZE
#endif
#ifdef CELL
	li	PREC,  -4 * SIZE
#endif
#else
/* Normal prefetch */
#ifdef PPC970
	li	PREC,   4 * SIZE
#endif
#ifdef POWER4
	li	PREC,   4 * SIZE   /* is 12 best? */
#endif
#ifdef POWER5
	li	PREC,   3 * SIZE
#endif
#endif

#else

#ifdef linux
#ifndef __64BIT__
	mr	PREA,  r10	
	lwz	PREB,   8 + STACKSIZE(SP)
	lwz	PREC,  12 + STACKSIZE(SP)
#else
	ld	PREA,  112 + STACKSIZE(SP)
	ld	PREB,  120 + STACKSIZE(SP)
	ld	PREC,  128 + STACKSIZE(SP)
#endif
#endif

#if defined(_AIX) || defined(__APPLE__)
#ifdef __64BIT__
	ld	PREA,  112 + STACKSIZE(SP)
	ld	PREB,  120 + STACKSIZE(SP)
	ld	PREC,  128 + STACKSIZE(SP)
#else
#ifdef DOUBLE
	lwz	PREA,   60 + STACKSIZE(SP)
	lwz	PREB,   64 + STACKSIZE(SP)
	lwz	PREC,   68 + STACKSIZE(SP)
#else
	lwz	PREA,   56 + STACKSIZE(SP)
	lwz	PREB,   60 + STACKSIZE(SP)
	lwz	PREC,   64 + STACKSIZE(SP)
#endif
#endif
#endif

#endif

#ifndef PREFETCHTEST
#ifdef PPC970
#ifdef ALLOC_HUGETLB
	li	PREA,   (16 *  5 * SIZE | 1)
	li	PREB,   (16 *  5 * SIZE | 3)
#else
	li	PREA,   (16 * 14 * SIZE | 1)
	li	PREB,   (16 *  8 * SIZE | 3)
#endif
#endif
#ifdef POWER4
#ifdef ALLOC_HUGETLB
	li	PREA,   (16 *  1 * SIZE + 16)
	li	PREB,   (16 *  1 * SIZE + 16)
#else
	li	PREA,   (16 *  2 * SIZE + 16)
	li	PREB,   (16 *  2 * SIZE + 16)
#endif
#endif
#ifdef POWER5
#ifdef ALLOC_HUGETLB
	li	PREA,   (16 *  7 * SIZE | 1)
	li	PREB,   (16 *  7 * SIZE | 3)
#else
	li	PREA,   (16 * 12 * SIZE | 1)
	li	PREB,   (16 *  6 * SIZE | 3)
#endif
#endif
#ifdef CELL
	li	PREA,   (16 * 12 * SIZE)
	li	PREB,   (16 * 12 * SIZE)
#endif
#endif

	lfs	f0, FZERO

	srawi.	J, N,  2
	ble	LL(40)
	.align 4

LL(10):

#ifdef RT
	slwi	r0, K, 2 + BASE_SHIFT
	sub	B, B, r0

	slwi	r0, LDC, 2
	sub	C, C, r0
#endif

	mr	CO1, C
	add	CO2, C,  LDC
	add	CO3, CO2, LDC
	add	CO4, CO3, LDC

#ifdef LN
	add	KK, M, OFFSET
#endif

#ifdef LT
	mr	KK, OFFSET
#endif

 	fmr	f1,  f0
	fmr	f2,  f0
	fmr	f3,  f0
	fmr	f4,  f0
	fmr	f5,  f0
	fmr	f6,  f0
	fmr	f7,  f0
	fmr	f8,  f0
	fmr	f9,  f0
	fmr	f10, f0
	fmr	f11, f0
	fmr	f12, f0
	fmr	f13, f0
	fmr	f14, f0
	fmr	f15, f0
	
	srawi.	I, M,  2

#if defined(LN) || defined(RT)
	mr	AORIG, A
#else
	mr	AO, A
#endif
#ifndef RT
	add	C,  CO4, LDC
#endif
	ble	LL(20)
	.align 4

LL(11):
#if defined(LT) || defined(RN)
	LFD	f16,  0 * SIZE(AO)
	LFD	f17,  1 * SIZE(AO)
	LFD	f18,  2 * SIZE(AO)
	LFD	f19,  3 * SIZE(AO)

	LFD	f20,  0 * SIZE(B)
	LFD	f21,  1 * SIZE(B)
	LFD	f22,  2 * SIZE(B)
	LFD	f23,  3 * SIZE(B)

	LFD	f24,  4 * SIZE(AO)
	LFD	f25,  5 * SIZE(AO)
	LFD	f26,  6 * SIZE(AO)

	LFD	f28,  4 * SIZE(B)
	LFD	f29,  5 * SIZE(B)
	LFD	f30,  6 * SIZE(B)

	dcbtst	CO1, PREC
	dcbtst	CO2, PREC
	dcbtst	CO3, PREC
	dcbtst	CO4, PREC
	
	srawi.	r0, KK,  2
	mtspr	CTR, r0
	mr	BO,  B
#else

#ifdef LN
	slwi	r0,   K,  2 + BASE_SHIFT
	sub	AORIG, AORIG, r0
#endif

	slwi	TEMP, KK, 2 + BASE_SHIFT
	add	AO, AORIG, TEMP
	add	BO, B,     TEMP

	sub	TEMP, K, KK

	LFD	f16,  0 * SIZE(AO)
	LFD	f17,  1 * SIZE(AO)
	LFD	f18,  2 * SIZE(AO)
	LFD	f19,  3 * SIZE(AO)

	LFD	f20,  0 * SIZE(BO)
	LFD	f21,  1 * SIZE(BO)
	LFD	f22,  2 * SIZE(BO)
	LFD	f23,  3 * SIZE(BO)

	dcbt	CO1, PREC
	dcbt	CO2, PREC
	dcbt	CO3, PREC
	dcbt	CO4, PREC

	srawi.	r0, TEMP,  2
	mtspr	CTR, r0
#endif
	ble	LL(15)
	.align 4

#define NOP1   mr	r18, r18
#define NOP2   mr	r19, r19

LL(12):
	FMADD	f0,  f16, f20, f0
	dcbt	AO, PREA
	FMADD	f4,  f16, f21, f4
	dcbt	BO, PREB
	FMADD	f8,  f16, f22, f8
	LFD	f31,  7 * SIZE(BO)
	FMADD	f12, f16, f23, f12
	LFD	f27,  7 * SIZE(AO)

	FMADD	f1,  f17, f20, f1
	LFD	f16,  8 * SIZE(AO)
	FMADD	f5,  f17, f21, f5
	NOP2
	FMADD	f9,  f17, f22, f9
	NOP1
	FMADD	f13, f17, f23, f13
	LFD	f17,  9 * SIZE(AO)

	FMADD	f2,  f18, f20, f2
	NOP1
	FMADD	f6,  f18, f21, f6
	NOP2
	FMADD	f10, f18, f22, f10
	NOP1
	FMADD	f14, f18, f23, f14
	LFD	f18, 10 * SIZE(AO)

	FMADD	f3,  f19, f20, f3
	LFD	f20,  8 * SIZE(BO)
	FMADD	f7,  f19, f21, f7
	LFD	f21,  9 * SIZE(BO)
	FMADD	f11, f19, f22, f11
	LFD	f22, 10 * SIZE(BO)
	FMADD	f15, f19, f23, f15
	LFD	f19, 11 * SIZE(AO)

	FMADD	f0,  f24, f28, f0
	LFD	f23, 11 * SIZE(BO)
	FMADD	f4,  f24, f29, f4
	NOP2
	FMADD	f8,  f24, f30, f8
	NOP1
	FMADD	f12, f24, f31, f12
	LFD	f24, 12 * SIZE(AO)

	FMADD	f1,  f25, f28, f1
	NOP1
	FMADD	f5,  f25, f29, f5
	NOP2
	FMADD	f9,  f25, f30, f9
	NOP1
	FMADD	f13, f25, f31, f13
	LFD	f25, 13 * SIZE(AO)

	FMADD	f2,  f26, f28, f2
	NOP1
	FMADD	f6,  f26, f29, f6
	NOP2
	FMADD	f10, f26, f30, f10
	NOP1
	FMADD	f14, f26, f31, f14
	LFD	f26, 14 * SIZE(AO)

	FMADD	f3,  f27, f28, f3
	LFD	f28, 12 * SIZE(BO)
	FMADD	f7,  f27, f29, f7
	LFD	f29, 13 * SIZE(BO)
	FMADD	f11, f27, f30, f11
	LFD	f30, 14 * SIZE(BO)
	FMADD	f15, f27, f31, f15
	LFD	f27, 15 * SIZE(AO)

	FMADD	f0,  f16, f20, f0
	LFD	f31, 15 * SIZE(BO)
	FMADD	f4,  f16, f21, f4
	NOP2
	FMADD	f8,  f16, f22, f8
	NOP1
	FMADD	f12, f16, f23, f12
	LFD	f16, 16 * SIZE(AO)

	FMADD	f1,  f17, f20, f1
	NOP1
	FMADD	f5,  f17, f21, f5
	NOP2
	FMADD	f9,  f17, f22, f9
	NOP1
	FMADD	f13, f17, f23, f13
	LFD	f17, 17 * SIZE(AO)

	FMADD	f2,  f18, f20, f2
	NOP1
	FMADD	f6,  f18, f21, f6
	NOP2
	FMADD	f10, f18, f22, f10
	NOP1
	FMADD	f14, f18, f23, f14
	LFD	f18, 18 * SIZE(AO)

	FMADD	f3,  f19, f20, f3
	LFD	f20, 16 * SIZE(BO)
	FMADD	f7,  f19, f21, f7
	LFD	f21, 17 * SIZE(BO)
	FMADD	f11, f19, f22, f11
	LFD	f22, 18 * SIZE(BO)
	FMADD	f15, f19, f23, f15
	LFD	f19, 19 * SIZE(AO)

	FMADD	f0,  f24, f28, f0
	LFD	f23, 19 * SIZE(BO)
	FMADD	f4,  f24, f29, f4
	NOP2
	FMADD	f8,  f24, f30, f8
	NOP1
	FMADD	f12, f24, f31, f12
	LFD	f24, 20 * SIZE(AO)

	FMADD	f1,  f25, f28, f1
	NOP1
	FMADD	f5,  f25, f29, f5
	NOP2
	FMADD	f9,  f25, f30, f9
	NOP1
	FMADD	f13, f25, f31, f13
	LFD	f25, 21 * SIZE(AO)

	FMADD	f2,  f26, f28, f2
	NOP1
	FMADD	f6,  f26, f29, f6
	NOP2
	FMADD	f10, f26, f30, f10
	NOP1
	FMADD	f14, f26, f31, f14
	LFD	f26, 22 * SIZE(AO)

	FMADD	f3,  f27, f28, f3
	LFD	f28, 20 * SIZE(BO)
	FMADD	f7,  f27, f29, f7
	LFD	f29, 21 * SIZE(BO)
	FMADD	f11, f27, f30, f11
	LFD	f30, 22 * SIZE(BO)
	FMADD	f15, f27, f31, f15
	addi	AO, AO, 16 * SIZE

	addi	BO, BO, 16 * SIZE
	bdnz	LL(12)
	.align 4

LL(15):
#if defined(LT) || defined(RN)
	andi.	r0, KK,  3
#else
	andi.	r0, TEMP, 3
#endif
	mtspr	CTR, r0
	ble+	LL(18)
	.align 4

LL(16):
	FMADD	f0,  f16, f20, f0
	FMADD	f5,  f17, f21, f5
	FMADD	f10, f18, f22, f10
	FMADD	f15, f19, f23, f15

	FMADD	f1,  f17, f20, f1
	FMADD	f2,  f18, f20, f2
	FMADD	f3,  f19, f20, f3
	FMADD	f4,  f16, f21, f4

	FMADD	f6,  f18, f21, f6
	FMADD	f7,  f19, f21, f7
	FMADD	f8,  f16, f22, f8
	FMADD	f9,  f17, f22, f9

	FMADD	f11, f19, f22, f11
	FMADD	f12, f16, f23, f12
	FMADD	f13, f17, f23, f13
	FMADD	f14, f18, f23, f14

	LFD	f16,  4 * SIZE(AO)
	LFD	f17,  5 * SIZE(AO)
	LFD	f18,  6 * SIZE(AO)
	LFD	f19,  7 * SIZE(AO)

	LFD	f20,  4 * SIZE(BO)
	LFD	f21,  5 * SIZE(BO)
	LFD	f22,  6 * SIZE(BO)
	LFD	f23,  7 * SIZE(BO)

	addi	BO, BO,  4 * SIZE
	addi	AO, AO,  4 * SIZE
	bdnz	LL(16)
	.align 4

LL(18):
#if defined(LN) || defined(RT)
	subi	r0, KK, 4
	slwi	r0, r0, 2 + BASE_SHIFT
	add	AO, AORIG, r0
	add	BO, B,     r0
#endif

#if defined(LN) || defined(LT)
	LFD	f16,  0 * SIZE(BO)
	LFD	f17,  1 * SIZE(BO)
	LFD	f18,  2 * SIZE(BO)
	LFD	f19,  3 * SIZE(BO)
 
	LFD	f20,  4 * SIZE(BO)
 	LFD	f21,  5 * SIZE(BO)
	LFD	f22,  6 * SIZE(BO)
	LFD	f23,  7 * SIZE(BO)

	LFD	f24,  8 * SIZE(BO)
	LFD	f25,  9 * SIZE(BO)
	LFD	f26, 10 * SIZE(BO)
	LFD	f27, 11 * SIZE(BO)

	LFD	f28, 12 * SIZE(BO)
	LFD	f29, 13 * SIZE(BO)
	LFD	f30, 14 * SIZE(BO)
	LFD	f31, 15 * SIZE(BO)

	FSUB	f0,  f16, f0
	FSUB	f4,  f17, f4
	FSUB	f8,  f18, f8
	FSUB	f12, f19, f12

	FSUB	f1,  f20, f1
	FSUB	f5,  f21, f5
	FSUB	f9,  f22, f9
	FSUB	f13, f23, f13

	FSUB	f2,  f24, f2
	FSUB	f6,  f25, f6
	FSUB	f10, f26, f10
	FSUB	f14, f27, f14

	FSUB	f3,  f28, f3
	FSUB	f7,  f29, f7
	FSUB	f11, f30, f11
	FSUB	f15, f31, f15
#else
	LFD	f16,  0 * SIZE(AO)
	LFD	f17,  1 * SIZE(AO)
	LFD	f18,  2 * SIZE(AO)
	LFD	f19,  3 * SIZE(AO)
 
	LFD	f20,  4 * SIZE(AO)
 	LFD	f21,  5 * SIZE(AO)
	LFD	f22,  6 * SIZE(AO)
	LFD	f23,  7 * SIZE(AO)

	LFD	f24,  8 * SIZE(AO)
	LFD	f25,  9 * SIZE(AO)
	LFD	f26, 10 * SIZE(AO)
	LFD	f27, 11 * SIZE(AO)

	LFD	f28, 12 * SIZE(AO)
	LFD	f29, 13 * SIZE(AO)
	LFD	f30, 14 * SIZE(AO)
	LFD	f31, 15 * SIZE(AO)

	FSUB	f0,  f16, f0
	FSUB	f1,  f17, f1
	FSUB	f2,  f18, f2
	FSUB	f3,  f19, f3

	FSUB	f4,  f20, f4
	FSUB	f5,  f21, f5
	FSUB	f6,  f22, f6
	FSUB	f7,  f23, f7

	FSUB	f8,  f24, f8
	FSUB	f9,  f25, f9
	FSUB	f10, f26, f10
	FSUB	f11, f27, f11

	FSUB	f12, f28, f12
	FSUB	f13, f29, f13
	FSUB	f14, f30, f14
	FSUB	f15, f31, f15
#endif

#ifdef LN
	LFD	f16, 15 * SIZE(AO)
	LFD	f17, 14 * SIZE(AO)
	LFD	f18, 13 * SIZE(AO)
	LFD	f19, 12 * SIZE(AO)

	FMUL	f3,  f16, f3
	FMUL	f7,  f16, f7
	FMUL	f11, f16, f11
	FMUL	f15, f16, f15

	FNMSUB	f2,  f17, f3,  f2
	FNMSUB	f6,  f17, f7,  f6
	FNMSUB	f10, f17, f11, f10
	FNMSUB	f14, f17, f15, f14

	FNMSUB	f1,  f18, f3,  f1
	FNMSUB	f5,  f18, f7,  f5
	FNMSUB	f9,  f18, f11, f9
	FNMSUB	f13, f18, f15, f13

	FNMSUB	f0,  f19, f3,  f0
	FNMSUB	f4,  f19, f7,  f4
	FNMSUB	f8,  f19, f11, f8
	FNMSUB	f12, f19, f15, f12

	LFD	f16, 10 * SIZE(AO)
	LFD	f17,  9 * SIZE(AO)
	LFD	f18,  8 * SIZE(AO)
	LFD	f19,  5 * SIZE(AO)

	FMUL	f2,  f16, f2
	FMUL	f6,  f16, f6
	FMUL	f10, f16, f10
	FMUL	f14, f16, f14

	LFD	f20,  4 * SIZE(AO)
	LFD	f21,  0 * SIZE(AO)

	FNMSUB	f1,  f17, f2,  f1
	FNMSUB	f5,  f17, f6,  f5
	FNMSUB	f9,  f17, f10, f9
	FNMSUB	f13, f17, f14,  f13

	FNMSUB	f0,  f18, f2,  f0
	FNMSUB	f4,  f18, f6,  f4
	FNMSUB	f8,  f18, f10, f8
	FNMSUB	f12, f18, f14, f12

	FMUL	f1,  f19, f1
	FMUL	f5,  f19, f5
	FMUL	f9,  f19, f9
	FMUL	f13, f19, f13

	FNMSUB	f0,  f20, f1,  f0
	FNMSUB	f4,  f20, f5,  f4
	FNMSUB	f8,  f20, f9,  f8
	FNMSUB	f12, f20, f13, f12

	FMUL	f0,  f21, f0
	FMUL	f4,  f21, f4
	FMUL	f8,  f21, f8
	FMUL	f12, f21, f12
#endif

#ifdef LT
	LFD	f16,  0 * SIZE(AO)
	LFD	f17,  1 * SIZE(AO)
	LFD	f18,  2 * SIZE(AO)
	LFD	f19,  3 * SIZE(AO)

	FMUL	f0,  f16, f0
	FMUL	f4,  f16, f4
	FMUL	f8,  f16, f8
	FMUL	f12, f16, f12

	FNMSUB	f1,  f17, f0,  f1
	FNMSUB	f5,  f17, f4,  f5
	FNMSUB	f9,  f17, f8,  f9
	FNMSUB	f13, f17, f12, f13

	FNMSUB	f2,  f18, f0,  f2
	FNMSUB	f6,  f18, f4,  f6
	FNMSUB	f10, f18, f8,  f10
	FNMSUB	f14, f18, f12, f14

	FNMSUB	f3,  f19, f0,  f3
	FNMSUB	f7,  f19, f4,  f7
	FNMSUB	f11, f19, f8,  f11
	FNMSUB	f15, f19, f12, f15

	LFD	f16,  5 * SIZE(AO)
	LFD	f17,  6 * SIZE(AO)
	LFD	f18,  7 * SIZE(AO)
	LFD	f19, 10 * SIZE(AO)

	FMUL	f1,  f16, f1
	FMUL	f5,  f16, f5
	FMUL	f9,  f16, f9
	FMUL	f13, f16, f13

	LFD	f20, 11 * SIZE(AO)
	LFD	f21, 15 * SIZE(AO)

	FNMSUB	f2,  f17, f1,  f2
	FNMSUB	f6,  f17, f5,  f6
	FNMSUB	f10, f17, f9,  f10
	FNMSUB	f14, f17, f13, f14

	FNMSUB	f3,  f18, f1,  f3
	FNMSUB	f7,  f18, f5,  f7
	FNMSUB	f11, f18, f9,  f11
	FNMSUB	f15, f18, f13, f15

	FMUL	f2,  f19, f2
	FMUL	f6,  f19, f6
	FMUL	f10, f19, f10
	FMUL	f14, f19, f14

	FNMSUB	f3,  f20, f2,  f3
	FNMSUB	f7,  f20, f6,  f7
	FNMSUB	f11, f20, f10, f11
	FNMSUB	f15, f20, f14, f15

	FMUL	f3,  f21, f3
	FMUL	f7,  f21, f7
	FMUL	f11, f21, f11
	FMUL	f15, f21, f15
#endif

#ifdef RN
	LFD	f16,  0 * SIZE(BO)
	LFD	f17,  1 * SIZE(BO)
	LFD	f18,  2 * SIZE(BO)
	LFD	f19,  3 * SIZE(BO)

	FMUL	f0,  f16, f0
	FMUL	f1,  f16, f1
	FMUL	f2,  f16, f2
	FMUL	f3,  f16, f3

	FNMSUB	f4,  f17, f0,  f4
	FNMSUB	f5,  f17, f1,  f5
	FNMSUB	f6,  f17, f2,  f6
	FNMSUB	f7,  f17, f3,  f7

	FNMSUB	f8,  f18, f0,  f8
	FNMSUB	f9,  f18, f1,  f9
	FNMSUB	f10, f18, f2,  f10
	FNMSUB	f11, f18, f3,  f11

	FNMSUB	f12, f19, f0,  f12
	FNMSUB	f13, f19, f1,  f13
	FNMSUB	f14, f19, f2,  f14
	FNMSUB	f15, f19, f3,  f15

	LFD	f16,  5 * SIZE(BO)
	LFD	f17,  6 * SIZE(BO)
	LFD	f18,  7 * SIZE(BO)
	LFD	f19, 10 * SIZE(BO)

	FMUL	f4,  f16, f4
	FMUL	f5,  f16, f5
	FMUL	f6,  f16, f6
	FMUL	f7,  f16, f7

	LFD	f20, 11 * SIZE(BO)
	LFD	f21, 15 * SIZE(BO)

	FNMSUB	f8,  f17, f4,  f8
	FNMSUB	f9,  f17, f5,  f9
	FNMSUB	f10, f17, f6,  f10
	FNMSUB	f11, f17, f7,  f11

	FNMSUB	f12, f18, f4,  f12
	FNMSUB	f13, f18, f5,  f13
	FNMSUB	f14, f18, f6,  f14
	FNMSUB	f15, f18, f7,  f15

	FMUL	f8,  f19, f8
	FMUL	f9,  f19, f9
	FMUL	f10, f19, f10
	FMUL	f11, f19, f11

	FNMSUB	f12, f20, f8,  f12
	FNMSUB	f13, f20, f9,  f13
	FNMSUB	f14, f20, f10, f14
	FNMSUB	f15, f20, f11, f15

	FMUL	f12, f21, f12
	FMUL	f13, f21, f13
	FMUL	f14, f21, f14
	FMUL	f15, f21, f15
#endif

#ifdef RT