gemv_n.s

Optimized GotoBLAS libraries

/*********************************************************************/
/*                                                                   */
/*             Optimized BLAS libraries                              */
/*                     By Kazushige Goto <[e-mail]>     */
/*                                                                   */
/* Copyright (c) The University of Texas, 2005. All rights reserved. */
/* UNIVERSITY EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES CONCERNING  */
/* THIS SOFTWARE AND DOCUMENTATION, INCLUDING ANY WARRANTIES OF      */
/* MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE,              */
/* NON-INFRINGEMENT AND WARRANTIES OF PERFORMANCE, AND ANY WARRANTY  */
/* THAT MIGHT OTHERWISE ARISE FROM COURSE OF DEALING OR USAGE OF     */
/* TRADE. NO WARRANTY IS EITHER EXPRESS OR IMPLIED WITH RESPECT TO   */
/* THE USE OF THE SOFTWARE OR DOCUMENTATION.                         */
/* Under no circumstances shall University be liable for incidental, */
/* special, indirect, direct or consequential damages or loss of     */
/* profits, interruption of business, or related expenses which may  */
/* arise from use of Software or Documentation, including but not    */
/* limited to those resulting from defects in Software and/or        */
/* Documentation, or loss or inaccuracy of data of any kind.         */
/*********************************************************************/

#define ASSEMBLER
#include "common.h"

#ifndef NEEDPARAM
#ifndef DOUBLE
#include "sparam_n.h"
#else
#include "dparam_n.h"
#endif
#endif

#ifdef linux
#ifndef __64BIT__
#define M	r3
#define	N	r4
#define A	r6
#define LDA	r7
#define X	r8
#define	INCX	r9
#define	Y	r10
#define	INCY	r5
#else
#define M	r3
#define	N	r4
#define A	r7
#define LDA	r8
#define X	r9
#define	INCX	r10
#define	Y	r5
#define	INCY	r6
#endif
#endif

#if defined(_AIX) || defined(__APPLE__)
#if !defined(__64BIT__) && defined(DOUBLE)
#define M	r3
#define	N	r4
#define A	r8
#define LDA	r9
#define X	r10
#define	INCX	r5
#define	Y	r6
#define	INCY	r7
#else
#define M	r3
#define	N	r4
#define A	r7
#define LDA	r8
#define X	r9
#define	INCX	r10
#define	Y	r5
#define	INCY	r6
#endif
#endif

#define I	r11
#define	J	r12

#define AO1	r14
#define AO2	r15
#define AO3	r16
#define AO4	r17
#define AO5	r18
#define AO6	r19
#define AO7	r20
#define AO8	r21
#define LDA8	r22

#define	Y1	r23
#define	PREA	r24
#define	PREC	r25
#define YY	r26
#define BUFFER	r27

#define y01 f0
#define y02 f1
#define y03 f2
#define y04 f3
#define y05 f4
#define y06 f5
#define y07 f6
#define y08 f7
#define y09 f8
#define y10 f9
#define y11 f10
#define y12 f11
#define y13 f12
#define y14 f13
#define y15 f14
#define y16 f15

#define alpha1 f16
#define alpha2 f17
#define alpha3 f18
#define alpha4 f19
#define alpha5 f20
#define alpha6 f21
#define alpha7 f22
#define alpha8 f23

#define a1     f24
#define a2     f25
#define a3     f26
#define a4     f27
#define a5     f28
#define a6     f29
#define a7     f30
#define a8     f31

#define alpha  f31

#if defined(PPCG4)
#define PREFETCHSIZE_A  24
#define PREFETCHSIZE_C  16
#endif

#if defined(PPC440) || defined(PPC440FP2)
#define PREFETCHSIZE_A  24
#define PREFETCHSIZE_C  16
#endif

#ifdef PPC970
#define PREFETCHSIZE_A  16
#define PREFETCHSIZE_C  16
#endif

#ifdef CELL
#define PREFETCHSIZE_A  16
#define PREFETCHSIZE_C  16
#endif

#ifdef POWER4
#define PREFETCHSIZE_A  16
#define PREFETCHSIZE_C  16
#endif

#ifdef POWER5
#define PREFETCHSIZE_A  24
#define PREFETCHSIZE_C  24
#endif

#ifndef NEEDPARAM

#ifndef __64BIT__
#define STACKSIZE 224
#define ALPHA     200(SP)
#define	FZERO	  208(SP)
#else
#define STACKSIZE 280
#define ALPHA     256(SP)
#define FZERO	  264(SP)
#endif

	PROLOGUE
	PROFCODE

	addi	SP,   SP, -STACKSIZE
	li	r0,   0

	stfd	f14,     0(SP)
	stfd	f15,     8(SP)
	stfd	f16,    16(SP)
	stfd	f17,    24(SP)
	stfd	f18,    32(SP)
	stfd	f19,    40(SP)
	stfd	f20,    48(SP)
	stfd	f21,    56(SP)
	stfd	f22,    64(SP)
	stfd	f23,    72(SP)
	stfd	f24,    80(SP)
	stfd	f25,    88(SP)
	stfd	f26,    96(SP)
	stfd	f27,   104(SP)
	stfd	f28,   112(SP)
	stfd	f29,   120(SP)
	stfd	f30,   128(SP)
	stfd	f31,   136(SP)

#ifdef __64BIT__
	std	r0,    FZERO
	std	r14,   144(SP)
	std	r15,   152(SP)
	std	r16,   160(SP)
	std	r17,   168(SP)
	std	r18,   176(SP)
	std	r19,   184(SP)
	std	r20,   192(SP)
	std	r21,   200(SP)
	std	r22,   208(SP)
	std	r23,   216(SP)
	std	r24,   224(SP)
	std	r25,   232(SP)
	std	r26,   240(SP)
	std	r27,   248(SP)
#else
	stw	r0,    0 + FZERO
	stw	r0,    4 + FZERO
	stw	r14,   144(SP)
	stw	r15,   148(SP)
	stw	r16,   152(SP)
	stw	r17,   156(SP)
	stw	r18,   160(SP)
	stw	r19,   164(SP)
	stw	r20,   168(SP)
	stw	r21,   172(SP)
	stw	r22,   176(SP)
	stw	r23,   180(SP)
	stw	r24,   184(SP)
	stw	r25,   188(SP)
	stw	r26,   192(SP)
	stw	r27,   196(SP)
#endif

#ifdef linux
#ifndef __64BIT__
	lwz	INCY,      8 + STACKSIZE(SP)
	lwz	BUFFER,  12 + STACKSIZE(SP)
#else
	ld	Y,       112 + STACKSIZE(SP)
	ld	INCY,    120 + STACKSIZE(SP)
	ld	BUFFER,  128 + STACKSIZE(SP)
#endif
#endif

#if defined(_AIX) || defined(__APPLE__)
#ifndef __64BIT__
#ifdef DOUBLE
	lwz	INCX,    56 + STACKSIZE(SP)
	lwz	Y,       60 + STACKSIZE(SP)
	lwz	INCY,    64 + STACKSIZE(SP)
	lwz	BUFFER,  68 + STACKSIZE(SP)
#else
	lwz	Y,       56 + STACKSIZE(SP)
	lwz	INCY,    60 + STACKSIZE(SP)
	lwz	BUFFER,  64 + STACKSIZE(SP)
#endif
#else
	ld	Y,       112 + STACKSIZE(SP)
	ld	INCY,    120 + STACKSIZE(SP)
	ld	BUFFER,  128 + STACKSIZE(SP)
#endif
#endif

	stfd	f1, ALPHA
	fmr	alpha, f1

	slwi	LDA8, LDA,  BASE_SHIFT + 3
	slwi	LDA,  LDA,  BASE_SHIFT
	slwi	INCX, INCX, BASE_SHIFT
	slwi	INCY, INCY, BASE_SHIFT

	li	PREA, PREFETCHSIZE_A * SIZE
	li	PREC, PREFETCHSIZE_C * SIZE

	cmpwi	cr0, M, 0
	ble-	LL(999)

	cmpwi	cr0, N, 0
	ble-	LL(999)

	mr	YY, Y
	lfd	f0, FZERO

	cmpi	cr0, 0, INCY, SIZE
	beq	LL(10)

	mr	YY, BUFFER
	mr	Y1, BUFFER

	addi	r0, M,  7
	srawi.	r0, r0, 3
	mtspr	CTR, r0
	.align 4

LL(02):
	STFD	f0, 0 * SIZE(Y1)
	STFD	f0, 1 * SIZE(Y1)
	STFD	f0, 2 * SIZE(Y1)
	STFD	f0, 3 * SIZE(Y1)
	STFD	f0, 4 * SIZE(Y1)
	STFD	f0, 5 * SIZE(Y1)
	STFD	f0, 6 * SIZE(Y1)
	STFD	f0, 7 * SIZE(Y1)
	addi	Y1, Y1, 8 * SIZE
	bdnz	LL(02)
	.align 4

LL(10):
	srawi.	J, N, 3
	ble	LL(20)
	.align 4

LL(11):
	LFD	alpha1, 0 * SIZE(X)
	add	X, X, INCX
	LFD	alpha2, 0 * SIZE(X)
	add	X, X, INCX
	LFD	alpha3, 0 * SIZE(X)
	add	X, X, INCX
	LFD	alpha4, 0 * SIZE(X)
	add	X, X, INCX
	LFD	alpha5, 0 * SIZE(X)
	add	X, X, INCX
	LFD	alpha6, 0 * SIZE(X)
	add	X, X, INCX
	LFD	alpha7, 0 * SIZE(X)
	add	X, X, INCX
	LFD	alpha8, 0 * SIZE(X)
	add	X, X, INCX

	FMUL	alpha1, alpha, alpha1
	FMUL	alpha2, alpha, alpha2
	FMUL	alpha3, alpha, alpha3
	FMUL	alpha4, alpha, alpha4
	FMUL	alpha5, alpha, alpha5
	FMUL	alpha6, alpha, alpha6
	FMUL	alpha7, alpha, alpha7
	FMUL	alpha8, alpha, alpha8

	mr	AO1, A
	add	AO2, A,   LDA
	add	AO3, AO2, LDA
	add	AO4, AO3, LDA
	add	AO5, AO4, LDA
	add	AO6, AO5, LDA
	add	AO7, AO6, LDA
	add	AO8, AO7, LDA
	add	A,   AO8, LDA

	mr	Y1, YY

	srawi.	r0,  M, 4
	mtspr	CTR, r0
	ble	LL(15)

	LFD	y01,  0 * SIZE(Y1)
	LFD	y02,  1 * SIZE(Y1)
	LFD	y03,  2 * SIZE(Y1)
	LFD	y04,  3 * SIZE(Y1)
	LFD	y05,  4 * SIZE(Y1)
	LFD	y06,  5 * SIZE(Y1)
	LFD	y07,  6 * SIZE(Y1)
	LFD	y08,  7 * SIZE(Y1)

	LFD	a1,  0 * SIZE(AO1)
	LFD	a2,  1 * SIZE(AO1)
	LFD	a3,  2 * SIZE(AO1)
	LFD	a4,  3 * SIZE(AO1)
	LFD	a5,  4 * SIZE(AO1)
	LFD	a6,  5 * SIZE(AO1)
	LFD	a7,  6 * SIZE(AO1)
	LFD	a8,  7 * SIZE(AO1)

	LFD	y09,  8 * SIZE(Y1)
	LFD	y10,  9 * SIZE(Y1)
	LFD	y11, 10 * SIZE(Y1)
	LFD	y12, 11 * SIZE(Y1)
	LFD	y13, 12 * SIZE(Y1)
	LFD	y14, 13 * SIZE(Y1)
	LFD	y15, 14 * SIZE(Y1)
	LFD	y16, 15 * SIZE(Y1)

	FMADD	y01, alpha1, a1, y01
	FMADD	y02, alpha1, a2, y02
	FMADD	y03, alpha1, a3, y03
	FMADD	y04, alpha1, a4, y04

	LFD	a1,  8 * SIZE(AO1)
	LFD	a2,  9 * SIZE(AO1)
	LFD	a3, 10 * SIZE(AO1)
	LFD	a4, 11 * SIZE(AO1)

	FMADD	y05, alpha1, a5, y05
	FMADD	y06, alpha1, a6, y06
	FMADD	y07, alpha1, a7, y07
	FMADD	y08, alpha1, a8, y08

	LFD	a5, 12 * SIZE(AO1)
	LFD	a6, 13 * SIZE(AO1)
	LFD	a7, 14 * SIZE(AO1)
	LFD	a8, 15 * SIZE(AO1)

	addi	AO1, AO1, 16 * SIZE
	nop
	nop
	PREFETCH_A1

	FMADD	y09, alpha1, a1, y09
	FMADD	y10, alpha1, a2, y10
	FMADD	y11, alpha1, a3, y11
	FMADD	y12, alpha1, a4, y12

	LFD	a1,  0 * SIZE(AO2)
	LFD	a2,  1 * SIZE(AO2)
	LFD	a3,  2 * SIZE(AO2)
	LFD	a4,  3 * SIZE(AO2)

	FMADD	y13, alpha1, a5, y13
	FMADD	y14, alpha1, a6, y14
	FMADD	y15, alpha1, a7, y15
	FMADD	y16, alpha1, a8, y16

	LFD	a5,  4 * SIZE(AO2)
	LFD	a6,  5 * SIZE(AO2)
	LFD	a7,  6 * SIZE(AO2)
	LFD	a8,  7 * SIZE(AO2)

	FMADD	y01, alpha2, a1, y01
	FMADD	y02, alpha2, a2, y02
	FMADD	y03, alpha2, a3, y03
	FMADD	y04, alpha2, a4, y04

	LFD	a1,  8 * SIZE(AO2)
	LFD	a2,  9 * SIZE(AO2)
	LFD	a3, 10 * SIZE(AO2)
	LFD	a4, 11 * SIZE(AO2)

	FMADD	y05, alpha2, a5, y05
	FMADD	y06, alpha2, a6, y06
	FMADD	y07, alpha2, a7, y07
	FMADD	y08, alpha2, a8, y08

	LFD	a5, 12 * SIZE(AO2)
	LFD	a6, 13 * SIZE(AO2)
	LFD	a7, 14 * SIZE(AO2)
	LFD	a8, 15 * SIZE(AO2)

	addi	AO2, AO2, 16 * SIZE
	nop
	nop
	PREFETCH_A2

	FMADD	y09, alpha2, a1, y09
	FMADD	y10, alpha2, a2, y10
	FMADD	y11, alpha2, a3, y11
	FMADD	y12, alpha2, a4, y12

	LFD	a1,  0 * SIZE(AO3)
	LFD	a2,  1 * SIZE(AO3)
	LFD	a3,  2 * SIZE(AO3)
	LFD	a4,  3 * SIZE(AO3)

	FMADD	y13, alpha2, a5, y13
	FMADD	y14, alpha2, a6, y14
	FMADD	y15, alpha2, a7, y15
	FMADD	y16, alpha2, a8, y16

	LFD	a5,  4 * SIZE(AO3)
	LFD	a6,  5 * SIZE(AO3)
	LFD	a7,  6 * SIZE(AO3)
	LFD	a8,  7 * SIZE(AO3)

	FMADD	y01, alpha3, a1, y01
	FMADD	y02, alpha3, a2, y02
	FMADD	y03, alpha3, a3, y03
	FMADD	y04, alpha3, a4, y04

	LFD	a1,  8 * SIZE(AO3)
	LFD	a2,  9 * SIZE(AO3)
	LFD	a3, 10 * SIZE(AO3)
	LFD	a4, 11 * SIZE(AO3)

	FMADD	y05, alpha3, a5, y05
	FMADD	y06, alpha3, a6, y06
	FMADD	y07, alpha3, a7, y07
	FMADD	y08, alpha3, a8, y08

	LFD	a5, 12 * SIZE(AO3)
	LFD	a6, 13 * SIZE(AO3)
	LFD	a7, 14 * SIZE(AO3)
	LFD	a8, 15 * SIZE(AO3)

	addi	AO3, AO3, 16 * SIZE
	nop
	nop
	PREFETCH_A3

	FMADD	y09, alpha3, a1, y09
	FMADD	y10, alpha3, a2, y10
	FMADD	y11, alpha3, a3, y11
	FMADD	y12, alpha3, a4, y12

	LFD	a1,  0 * SIZE(AO4)
	LFD	a2,  1 * SIZE(AO4)
	LFD	a3,  2 * SIZE(AO4)
	LFD	a4,  3 * SIZE(AO4)

	FMADD	y13, alpha3, a5, y13
	FMADD	y14, alpha3, a6, y14
	FMADD	y15, alpha3, a7, y15
	FMADD	y16, alpha3, a8, y16

	LFD	a5,  4 * SIZE(AO4)
	LFD	a6,  5 * SIZE(AO4)
	LFD	a7,  6 * SIZE(AO4)
	LFD	a8,  7 * SIZE(AO4)

	FMADD	y01, alpha4, a1, y01
	FMADD	y02, alpha4, a2, y02
	FMADD	y03, alpha4, a3, y03
	FMADD	y04, alpha4, a4, y04

	LFD	a1,  8 * SIZE(AO4)
	LFD	a2,  9 * SIZE(AO4)
	LFD	a3, 10 * SIZE(AO4)
	LFD	a4, 11 * SIZE(AO4)

	FMADD	y05, alpha4, a5, y05
	FMADD	y06, alpha4, a6, y06
	FMADD	y07, alpha4, a7, y07
	FMADD	y08, alpha4, a8, y08

	LFD	a5, 12 * SIZE(AO4)
	LFD	a6, 13 * SIZE(AO4)
	LFD	a7, 14 * SIZE(AO4)
	LFD	a8, 15 * SIZE(AO4)

	addi	AO4, AO4, 16 * SIZE
	nop
	nop
	PREFETCH_A4

	FMADD	y09, alpha4, a1, y09
	FMADD	y10, alpha4, a2, y10
	FMADD	y11, alpha4, a3, y11
	FMADD	y12, alpha4, a4, y12

	LFD	a1,  0 * SIZE(AO5)
	LFD	a2,  1 * SIZE(AO5)
	LFD	a3,  2 * SIZE(AO5)
	LFD	a4,  3 * SIZE(AO5)

	FMADD	y13, alpha4, a5, y13
	FMADD	y14, alpha4, a6, y14
	FMADD	y15, alpha4, a7, y15
	FMADD	y16, alpha4, a8, y16

	LFD	a5,  4 * SIZE(AO5)
	LFD	a6,  5 * SIZE(AO5)
	LFD	a7,  6 * SIZE(AO5)
	LFD	a8,  7 * SIZE(AO5)

	FMADD	y01, alpha5, a1, y01
	FMADD	y02, alpha5, a2, y02
	FMADD	y03, alpha5, a3, y03
	FMADD	y04, alpha5, a4, y04

	LFD	a1,  8 * SIZE(AO5)
	LFD	a2,  9 * SIZE(AO5)
	LFD	a3, 10 * SIZE(AO5)
	LFD	a4, 11 * SIZE(AO5)

	FMADD	y05, alpha5, a5, y05
	FMADD	y06, alpha5, a6, y06
	FMADD	y07, alpha5, a7, y07
	FMADD	y08, alpha5, a8, y08

	LFD	a5, 12 * SIZE(AO5)
	LFD	a6, 13 * SIZE(AO5)
	LFD	a7, 14 * SIZE(AO5)
	LFD	a8, 15 * SIZE(AO5)

	addi	AO5, AO5, 16 * SIZE
	nop
	nop
	PREFETCH_A5

	FMADD	y09, alpha5, a1, y09
	FMADD	y10, alpha5, a2, y10
	FMADD	y11, alpha5, a3, y11
	FMADD	y12, alpha5, a4, y12

	LFD	a1,  0 * SIZE(AO6)
	LFD	a2,  1 * SIZE(AO6)
	LFD	a3,  2 * SIZE(AO6)
	LFD	a4,  3 * SIZE(AO6)

	FMADD	y13, alpha5, a5, y13
	FMADD	y14, alpha5, a6, y14
	FMADD	y15, alpha5, a7, y15
	FMADD	y16, alpha5, a8, y16

	LFD	a5,  4 * SIZE(AO6)
	LFD	a6,  5 * SIZE(AO6)
	LFD	a7,  6 * SIZE(AO6)
	LFD	a8,  7 * SIZE(AO6)

	FMADD	y01, alpha6, a1, y01
	FMADD	y02, alpha6, a2, y02
	FMADD	y03, alpha6, a3, y03
	FMADD	y04, alpha6, a4, y04

	LFD	a1,  8 * SIZE(AO6)
	LFD	a2,  9 * SIZE(AO6)
	LFD	a3, 10 * SIZE(AO6)