spictr.v

鉴于SPI传输的大量应用

/****************************************************;
;   Module	:   PllCtr	                 	  		   	 ;
;   Usage		:   transfer the input data_in to PLL	   ;
;		note		:																			   ;
;**************************************************/
module PllCtr(clk,enable,data_in,
							pll_clk,pll_din,pll_le
							);

input		clk,enable;
input		[23:0]data_in;

output	pll_clk,pll_din,pll_le;

reg	pll_clk,pll_din,pll_le;
reg	[23:0]old_Dvar,new_Dvar;
reg [4:0]clk_Cnt;
reg pre_Start,pre_Le,pre_Pll_clk,pre_Ena;


always @ (posedge clk)
if (!enable)
	new_Dvar<=0;
else
	if (!(pre_Start||pll_le||pll_clk||pre_Le)&&pre_Ena)
		new_Dvar<=data_in;
	else
		new_Dvar<=new_Dvar;

always @ (posedge clk)
if (!enable)
	pre_Ena<=0;
else 
	pre_Ena<=~pre_Ena;

		
always @ (posedge clk)
if (!enable)
	old_Dvar<=0;
else
	old_Dvar<=new_Dvar;
	
always @ (posedge clk)
if (!enable)
	pre_Start<=0;						//pre_Start also used as busy indication
else
	if (clk_Cnt!=23)				//ref clk,then pll_clk will be exactly 24 clk_Cnt
		if (old_Dvar!=new_Dvar)
			pre_Start<=1;
		else
			pre_Start<=pre_Start;
	else
		pre_Start<=0;
		

always @ (posedge clk)		//28M clk,then pll_CLK=14M
if (!enable)
	begin
	pre_Pll_clk<=0;	
	pll_clk<=0;
	end
else
	if (pre_Start)
		begin
		pre_Pll_clk<=~pre_Pll_clk;
		pll_clk<=pre_Pll_clk;
		end
	else
		begin
		pre_Pll_clk<=0;
		pll_clk<=pre_Pll_clk;
		end

always @ (posedge clk)		
if (!enable)
	clk_Cnt<=0;
else
	if (pll_clk)
		if (clk_Cnt<23)
			clk_Cnt<=clk_Cnt+1;
		else
			clk_Cnt<=0;
	else
		clk_Cnt<=clk_Cnt;

always @ (posedge clk)
if (!enable)
	begin
	pre_Le<=0;
	pll_le<=0;
	end
else
	begin
	pre_Le<=(!pre_Start&&pll_clk);
	pll_le<=pre_Le;								// to meet the t5,so delay pre_Le a clock.
	end
		
always @ (posedge clk)
if (!enable)
	pll_din<=0;
else
	if ((clk_Cnt==0)&&pre_Start)		//as the pll_din change at pll_clk==H and latch into shift_reg at posedge of pll_clk,	
		pll_din<=old_Dvar[23];									//so data_in[23:0] should send to din before the CASE(clk_Cnt) statement
	else if (pll_clk&&pre_Start)								//to meet hold/setup time,use pll_clk=H to get the bit of data_in[23:0]
		case (clk_Cnt)
		0:pll_din<=old_Dvar[22];
		1:pll_din<=old_Dvar[21];
		2:pll_din<=old_Dvar[20];
		3:pll_din<=old_Dvar[19];
		4:pll_din<=old_Dvar[18];
		5:pll_din<=old_Dvar[17];
		6:pll_din<=old_Dvar[16];
		7:pll_din<=old_Dvar[15];
		8:pll_din<=old_Dvar[14];
		9:pll_din<=old_Dvar[13];
		10:pll_din<=old_Dvar[12];
		11:pll_din<=old_Dvar[11];
		12:pll_din<=old_Dvar[10];
		13:pll_din<=old_Dvar[9];
		14:pll_din<=old_Dvar[8];
		15:pll_din<=old_Dvar[7];
		16:pll_din<=old_Dvar[6];
		17:pll_din<=old_Dvar[5];
		18:pll_din<=old_Dvar[4];
		19:pll_din<=old_Dvar[3];
		20:pll_din<=old_Dvar[2];
    21:pll_din<=old_Dvar[1];
    22:pll_din<=old_Dvar[0];
    23:pll_din<=pll_din;								//by the reason before,at the point clk_Cnt=23 no din will latch into shift_reg,so hold din
		default:pll_din<=pll_din;
		endcase
	else
		pll_din<=pll_din;

		

 endmodule