top_sh.v

来自「插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现」· Verilog 代码 · 共 18 行

`timescale 1ns/10ps
module top_sh(data_in,clock,reset,data_out);

input clock,reset;
input [18:1] data_in;
output [18:1] data_out;

reg [18:1] data_out;

always@(posedge clock or negedge reset)
  begin
    if(!reset)
       data_out=0;
    else
       data_out=data_in;
  end
endmodule