📄 smic18io_stagger.v
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and _i2 (_n2,_n3,_n4); and _i4 (_n5,A,_n3,NEN); not _i5 (_n8,A); and _i7 (_n7,_n8,PEN,_n4); nor _i8 (_n1,_n2,_n5,_n7); not _i9 (_n12,PU); not _i10 (_n13,PD); and _i11 (_n11,_n12,_n13); rnmos _i12 (_n14,1'b1,1'b1); and _i13 (_n16,PU,PD); rpmos _i14 (_n17,1'b0,1'b0); and _i16 (_n19,_n12,PD); bufif1 _i17 (_n18,1'bx,_n19); nmos _i18 (_n15,_n17,_n16); pmos _i19 (_n15,_n18,_n16); nmos _i20 (_n10,_n14,_n11); pmos _i21 (_n10,_n15,_n11); nmos _i22 (_P,A,_n1); pmos _i23 (_P,_n10,_n1); nmos _i24 (P,_P,1'b1); or _i25 (_n22,SONOF,CONOF); and _i26 (D,P,_n22); specify (CONOF => D) = (0,0); (PEN => P) = (0,0,0,0,0,0); (PU => P) = (0,0,0,0,0,0); (PD => P) = (0,0,0,0,0,0); (SONOF => D) = (0,0); if(!CONOF&SONOF) (P => D) = (0,0); if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0); if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0); if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0); if(CONOF&!SONOF) (P => D) = (0,0); if(CONOF&SONOF) (P => D) = (0,0); if(NEN&!PD&PEN&!PU) (A => P) = (0,0); if(NEN&!PD&PEN&PU) (A => P) = (0,0); if(NEN&PD&PEN&!PU) (A => P) = (0,0); if(NEN&PD&PEN&PU) (A => P) = (0,0); ifnone (A => P) = (0,0,0,0,0,0); ifnone (NEN => P) = (0,0,0,0,0,0); ifnone (P => D) = (0,0); endspecifyendmodule`endcelldefine`celldefine// 4mA, fast slew rate, input-output pad, 5V tolerant// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)module PSBI4F (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF); output D; inout P; input A; input CONOF; input NEN; input PD; input PEN; input PU; input SONOF; wor P; not _i0 (_n3,PEN); not _i1 (_n4,NEN); and _i2 (_n2,_n3,_n4); and _i4 (_n5,A,_n3,NEN); not _i5 (_n8,A); and _i7 (_n7,_n8,PEN,_n4); nor _i8 (_n1,_n2,_n5,_n7); not _i9 (_n12,PU); not _i10 (_n13,PD); and _i11 (_n11,_n12,_n13); rnmos _i12 (_n14,1'b1,1'b1); and _i13 (_n16,PU,PD); rpmos _i14 (_n17,1'b0,1'b0); and _i16 (_n19,_n12,PD); bufif1 _i17 (_n18,1'bx,_n19); nmos _i18 (_n15,_n17,_n16); pmos _i19 (_n15,_n18,_n16); nmos _i20 (_n10,_n14,_n11); pmos _i21 (_n10,_n15,_n11); nmos _i22 (_P,A,_n1); pmos _i23 (_P,_n10,_n1); nmos _i24 (P,_P,1'b1); or _i25 (_n22,SONOF,CONOF); and _i26 (D,P,_n22); specify (CONOF => D) = (0,0); (PEN => P) = (0,0,0,0,0,0); (PU => P) = (0,0,0,0,0,0); (PD => P) = (0,0,0,0,0,0); (SONOF => D) = (0,0); if(!CONOF&SONOF) (P => D) = (0,0); if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0); if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0); if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0); if(CONOF&!SONOF) (P => D) = (0,0); if(CONOF&SONOF) (P => D) = (0,0); if(NEN&!PD&PEN&!PU) (A => P) = (0,0); if(NEN&!PD&PEN&PU) (A => P) = (0,0); if(NEN&PD&PEN&!PU) (A => P) = (0,0); if(NEN&PD&PEN&PU) (A => P) = (0,0); ifnone (A => P) = (0,0,0,0,0,0); ifnone (NEN => P) = (0,0,0,0,0,0); ifnone (P => D) = (0,0); endspecifyendmodule`endcelldefine`celldefine// 4mA, normal slew rate, input-output pad, 5V tolerant// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)module PSBI4N (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF); output D; inout P; input A; input CONOF; input NEN; input PD; input PEN; input PU; input SONOF; wor P; not _i0 (_n3,PEN); not _i1 (_n4,NEN); and _i2 (_n2,_n3,_n4); and _i4 (_n5,A,_n3,NEN); not _i5 (_n8,A); and _i7 (_n7,_n8,PEN,_n4); nor _i8 (_n1,_n2,_n5,_n7); not _i9 (_n12,PU); not _i10 (_n13,PD); and _i11 (_n11,_n12,_n13); rnmos _i12 (_n14,1'b1,1'b1); and _i13 (_n16,PU,PD); rpmos _i14 (_n17,1'b0,1'b0); and _i16 (_n19,_n12,PD); bufif1 _i17 (_n18,1'bx,_n19); nmos _i18 (_n15,_n17,_n16); pmos _i19 (_n15,_n18,_n16); nmos _i20 (_n10,_n14,_n11); pmos _i21 (_n10,_n15,_n11); nmos _i22 (_P,A,_n1); pmos _i23 (_P,_n10,_n1); nmos _i24 (P,_P,1'b1); or _i25 (_n22,SONOF,CONOF); and _i26 (D,P,_n22); specify (CONOF => D) = (0,0); (PEN => P) = (0,0,0,0,0,0); (PU => P) = (0,0,0,0,0,0); (PD => P) = (0,0,0,0,0,0); (SONOF => D) = (0,0); if(!CONOF&SONOF) (P => D) = (0,0); if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0); if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0); if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0); if(CONOF&!SONOF) (P => D) = (0,0); if(CONOF&SONOF) (P => D) = (0,0); if(NEN&!PD&PEN&!PU) (A => P) = (0,0); if(NEN&!PD&PEN&PU) (A => P) = (0,0); if(NEN&PD&PEN&!PU) (A => P) = (0,0); if(NEN&PD&PEN&PU) (A => P) = (0,0); ifnone (A => P) = (0,0,0,0,0,0); ifnone (NEN => P) = (0,0,0,0,0,0); ifnone (P => D) = (0,0); endspecifyendmodule`endcelldefine`celldefine// 4mA, slow slew rate, input-output pad, 5V tolerant// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)module PSBI4S (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF); output D; inout P; input A; input CONOF; input NEN; input PD; input PEN; input PU; input SONOF; wor P; not _i0 (_n3,PEN); not _i1 (_n4,NEN); and _i2 (_n2,_n3,_n4); and _i4 (_n5,A,_n3,NEN); not _i5 (_n8,A); and _i7 (_n7,_n8,PEN,_n4); nor _i8 (_n1,_n2,_n5,_n7); not _i9 (_n12,PU); not _i10 (_n13,PD); and _i11 (_n11,_n12,_n13); rnmos _i12 (_n14,1'b1,1'b1); and _i13 (_n16,PU,PD); rpmos _i14 (_n17,1'b0,1'b0); and _i16 (_n19,_n12,PD); bufif1 _i17 (_n18,1'bx,_n19); nmos _i18 (_n15,_n17,_n16); pmos _i19 (_n15,_n18,_n16); nmos _i20 (_n10,_n14,_n11); pmos _i21 (_n10,_n15,_n11); nmos _i22 (_P,A,_n1); pmos _i23 (_P,_n10,_n1); nmos _i24 (P,_P,1'b1); or _i25 (_n22,SONOF,CONOF); and _i26 (D,P,_n22); specify (CONOF => D) = (0,0); (PEN => P) = (0,0,0,0,0,0); (PU => P) = (0,0,0,0,0,0); (PD => P) = (0,0,0,0,0,0); (SONOF => D) = (0,0); if(!CONOF&SONOF) (P => D) = (0,0); if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0); if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0); if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0); if(CONOF&!SONOF) (P => D) = (0,0); if(CONOF&SONOF) (P => D) = (0,0); if(NEN&!PD&PEN&!PU) (A => P) = (0,0); if(NEN&!PD&PEN&PU) (A => P) = (0,0); if(NEN&PD&PEN&!PU) (A => P) = (0,0); if(NEN&PD&PEN&PU) (A => P) = (0,0); ifnone (A => P) = (0,0,0,0,0,0); ifnone (NEN => P) = (0,0,0,0,0,0); ifnone (P => D) = (0,0); endspecifyendmodule`endcelldefine`celldefine// 8mA, fast slew rate, input-output pad, 5V tolerant// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)module PSBI8F (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF); output D; inout P; input A; input CONOF; input NEN; input PD; input PEN; input PU; input SONOF; wor P; not _i0 (_n3,PEN); not _i1 (_n4,NEN); and _i2 (_n2,_n3,_n4); and _i4 (_n5,A,_n3,NEN); not _i5 (_n8,A); and _i7 (_n7,_n8,PEN,_n4); nor _i8 (_n1,_n2,_n5,_n7); not _i9 (_n12,PU); not _i10 (_n13,PD); and _i11 (_n11,_n12,_n13); rnmos _i12 (_n14,1'b1,1'b1); and _i13 (_n16,PU,PD); rpmos _i14 (_n17,1'b0,1'b0); and _i16 (_n19,_n12,PD); bufif1 _i17 (_n18,1'bx,_n19); nmos _i18 (_n15,_n17,_n16); pmos _i19 (_n15,_n18,_n16); nmos _i20 (_n10,_n14,_n11); pmos _i21 (_n10,_n15,_n11); nmos _i22 (_P,A,_n1); pmos _i23 (_P,_n10,_n1); nmos _i24 (P,_P,1'b1); or _i25 (_n22,SONOF,CONOF); and _i26 (D,P,_n22); specify (CONOF => D) = (0,0); (PEN => P) = (0,0,0,0,0,0); (PU => P) = (0,0,0,0,0,0); (PD => P) = (0,0,0,0,0,0); (SONOF => D) = (0,0); if(!CONOF&SONOF) (P => D) = (0,0); if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0); if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0); if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0); if(CONOF&!SONOF) (P => D) = (0,0); if(CONOF&SONOF) (P => D) = (0,0); if(NEN&!PD&PEN&!PU) (A => P) = (0,0); if(NEN&!PD&PEN&PU) (A => P) = (0,0); if(NEN&PD&PEN&!PU) (A => P) = (0,0); if(NEN&PD&PEN&PU) (A => P) = (0,0); ifnone (A => P) = (0,0,0,0,0,0); ifnone (NEN => P) = (0,0,0,0,0,0); ifnone (P => D) = (0,0); endspecifyendmodule`endcelldefine`celldefine// 8mA, normal slew rate, input-output pad, 5V tolerant// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)module PSBI8N (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF); output D; inout P; input A; input CONOF; input NEN; input PD; input PEN; input PU; input SONOF; wor P; not _i0 (_n3,PEN); not _i1 (_n4,NEN); and _i2 (_n2,_n3,_n4); and _i4 (_n5,A,_n3,NEN); not _i5 (_n8,A); and _i7 (_n7,_n8,PEN,_n4); nor _i8 (_n1,_n2,_n5,_n7); not _i9 (_n12,PU); not _i10 (_n13,PD); and _i11 (_n11,_n12,_n13); rnmos _i12 (_n14,1'b1,1'b1); and _i13 (_n16,PU,PD); rpmos _i14 (_n17,1'b0,1'b0); and _i16 (_n19,_n12,PD); bufif1 _i17 (_n18,1'bx,_n19); nmos _i18 (_n15,_n17,_n16); pmos _i19 (_n15,_n18,_n16); nmos _i20 (_n10,_n14,_n11); pmos _i21 (_n10,_n15,_n11); nmos _i22 (_P,A,_n1); pmos _i23 (_P,_n10,_n1); nmos _i24 (P,_P,1'b1); or _i25 (_n22,SONOF,CONOF); and _i26 (D,P,_n22); specify (CONOF => D) = (0,0); (PEN => P) = (0,0,0,0,0,0); (PU => P) = (0,0,0,0,0,0); (PD => P) = (0,0,0,0,0,0); (SONOF => D) = (0,0); if(!CONOF&SONOF) (P => D) = (0,0); if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0); if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0); if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0); if(CONOF&!SONOF) (P => D) = (0,0); if(CONOF&SONOF) (P => D) = (0,0); if(NEN&!PD&PEN&!PU) (A => P) = (0,0); if(NEN&!PD&PEN&PU) (A => P) = (0,0); if(NEN&PD&PEN&!PU) (A => P) = (0,0); if(NEN&PD&PEN&PU) (A => P) = (0,0); ifnone (A => P) = (0,0,0,0,0,0); ifnone (NEN => P) = (0,0,0,0,0,0); ifnone (P => D) = (0,0); endspecifyendmodule`endcelldefine`celldefine// 8mA, slow slew rate, input-output pad, 5V tolerant// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)module PSBI8S (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF); output D; inout P; input A; input CONOF; input NEN; input PD; input PEN; input PU; input SONOF; wor P; not _i0 (_n3,PEN); not _i1 (_n4,NEN); and _i2 (_n2,_n3,_n4); and _i4 (_n5,A,_n3,NEN); not _i5 (_n8,A); and _i7 (_n7,_n8,PEN,_n4); nor _i8 (_n1,_n2,_n5,_n7); not _i9 (_n12,PU); not _i10 (_n13,PD); and _i11 (_n11,_n12,_n13); rnmos _i12 (_n14,1'b1,1'b1); and _i13 (_n16,PU,PD); rpmos _i14 (_n17,1'b0,1'b0); and _i16 (_n19,_n12,PD); bufif1 _i17 (_n18,1'bx,_n19); nmos _i18 (_n15,_n17,_n16); pmos _i19 (_n15,_n18,_n16); nmos _i20 (_n10,_n14,_n11); pmos _i21 (_n10,_n15,_n11); nmos _i22 (_P,A,_n1); pmos _i23 (_P,_n10,_n1); nmos _i24 (P,_P,1'b1); or _i25 (_n22,SONOF,CONOF); and _i26 (D,P,_n22); specify (CONOF => D) = (0,0); (PEN => P) = (0,0,0,0,0,0); (PU => P) = (0,0,0,0,0,0); (PD => P) = (0,0,0,0,0,0); (SONOF => D) = (0,0); if(!CONOF&SONOF) (P => D) = (0,0); if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0); if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0); if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0); if(CONOF&!SONOF) (P => D) = (0,0); if(CONOF&SONOF) (P => D) = (0,0); if(NEN&!PD&PEN&!PU) (A => P) = (0,0); if(NEN&!PD&PEN&PU) (A => P) = (0,0); if(NEN&PD&PEN&!PU) (A => P) = (0,0); if(NEN&PD&PEN&PU) (A => P) = (0,0); ifnone (A => P) = (0,0,0,0,0,0); ifnone (NEN => P) = (0,0,0,0,0,0); ifnone (P => D) = (0,0); endspecifyendmodule`endcelldefine`celldefine// Oscillator pad without resistor// XTALOUT = !(EO&XTALIN);CK = EI&XTALINmodule PSOSC14M (CK, XTALOUT, EI, EO, XTALIN); output CK; output XTALOUT; input EI; input EO; input XTALIN; nand _i0 (XTALOUT,EO,XTALIN); and _i1 (CK,EI,XTALIN); specify (EI => CK) = (0,0); (EO => XTALOUT) = (0,0); if(!EI) (XTALIN => XTALOUT) = (0,0); if(!EO) (XTALIN => CK) = (0,0); if(EI) (XTALIN => XTALOUT) = (0,0); if(EO) (XTALIN => CK) = (0,0); ifnone (XTALIN => CK) = (0,0); ifnone (XTALIN => XTALOUT) = (0,0); endspecifyendmodule`endcelldefine`celldefine// Oscillator pad with 2M ohm resistor// XTALOUT = EO ? !XTALIN : 'l';CK = EI&XTALINmodule PSOSCR14M (CK, XTALOUT, EI, EO, XTALIN); output CK; output XTALOUT; input EI; input EO; input XTALIN; not _i0 (_n1,XTALIN); rpmos _i1 (_n2, 1'b0, 1'b0); nmos _i2 (_XTALOUT, _n1, EO); pmos _i3 (_XTALOUT, _n2, EO); nmos _i4 (XTALOUT, _XTALOUT, 1'b1); and _i5 (CK,EI,XTALIN); specify if(!EI) (XTALIN => XTALOUT) = (0,0); if(!EO) (EI => CK) = (0,0); if(!EO) (XTALIN => CK) = (0,0); if(EI) (XTALIN => XTALOUT) = (0,0); if(EO) (EI => CK) = (0,0); if(EO) (XTALIN => CK) = (0,0); ifnone (EI => CK) = (0,0); ifnone (XTALIN => CK) = (0,0); ifnone (XTALIN => XTALOUT) = (0,0); endspecifyendmodule`endcelldefine`celldefinemodule PSVDDC (vdd); inout vdd; supply1 vdd;endmodule`endcelldefine`celldefinemodule PSVDDH (VDDH); inout VDDH; supply1 VDDH;endmodule`endcelldefine`celldefinemodule PSVDDO (VDDO); inout VDDO; supply1 VDDO;endmodule`endcelldefine`celldefinemodule PSVSSC (gnd); inout gnd; supply0 gnd;endmodule`endcelldefine`celldefinemodule PSVSSH (VSSH); inout VSSH; supply0 VSSH;endmodule`endcelldefine`celldefinemodule PSVSSO (VSSO); inout VSSO; supply0 VSSO;endmodule`endcelldefine⌨️ 快捷键说明
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