smic18io_stagger.v

插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现

// revision : 2.1
// date : "Mon Jan 20 09:28:05 CST 2003"
// generated by Verisilicon Microelectonics (Shanghai). 
`timescale 1ns/10ps
`celldefine
// 16mA, fast slew rate, input-output pad, 5V tolerant
// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)
module PSBI16F (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF);
	output D;
	inout  P;
	input  A;
	input  CONOF;
	input  NEN;
	input  PD;
	input  PEN;
	input  PU;
	input  SONOF;
	wor P;
	not _i0 (_n3,PEN);
	not _i1 (_n4,NEN);
	and _i2 (_n2,_n3,_n4);
	and _i4 (_n5,A,_n3,NEN);
	not _i5 (_n8,A);
	and _i7 (_n7,_n8,PEN,_n4);
	nor _i8 (_n1,_n2,_n5,_n7);
	not _i9 (_n12,PU);
	not _i10 (_n13,PD);
	and _i11 (_n11,_n12,_n13);
	rnmos _i12 (_n14,1'b1,1'b1);
	and _i13 (_n16,PU,PD);
	rpmos _i14 (_n17,1'b0,1'b0);
	and _i16 (_n19,_n12,PD);
	bufif1 _i17 (_n18,1'bx,_n19);
	nmos _i18 (_n15,_n17,_n16);
	pmos _i19 (_n15,_n18,_n16);
	nmos _i20 (_n10,_n14,_n11);
	pmos _i21 (_n10,_n15,_n11);
	nmos _i22 (_P,A,_n1);
	pmos _i23 (_P,_n10,_n1);
	nmos _i24 (P,_P,1'b1);
	or _i25 (_n22,SONOF,CONOF);
	and _i26 (D,P,_n22);
	specify
	
		(CONOF => D) = (0,0);
        (PEN => P) = (0,0,0,0,0,0);
        (PU => P) = (0,0,0,0,0,0);
        (PD => P) = (0,0,0,0,0,0);
        (SONOF => D) = (0,0);
	if(!CONOF&SONOF) (P => D) = (0,0);
	if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0);
	if(CONOF&!SONOF) (P => D) = (0,0);
	if(CONOF&SONOF) (P => D) = (0,0);
	if(NEN&!PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&!PD&PEN&PU) (A => P) = (0,0);
	if(NEN&PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&PD&PEN&PU) (A => P) = (0,0);
	ifnone (A => P) = (0,0,0,0,0,0);
	ifnone (NEN => P) = (0,0,0,0,0,0);
	ifnone (P => D) = (0,0);
	endspecify
endmodule
`endcelldefine
`celldefine
// 16 mA, normal slew rate, input-output pad, 5V tolerant
// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)
module PSBI16N (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF);
	output D;
	inout  P;
	input  A;
	input  CONOF;
	input  NEN;
	input  PD;
	input  PEN;
	input  PU;
	input  SONOF;
	wor P;
	not _i0 (_n3,PEN);
	not _i1 (_n4,NEN);
	and _i2 (_n2,_n3,_n4);
	and _i4 (_n5,A,_n3,NEN);
	not _i5 (_n8,A);
	and _i7 (_n7,_n8,PEN,_n4);
	nor _i8 (_n1,_n2,_n5,_n7);
	not _i9 (_n12,PU);
	not _i10 (_n13,PD);
	and _i11 (_n11,_n12,_n13);
	rnmos _i12 (_n14,1'b1,1'b1);
	and _i13 (_n16,PU,PD);
	rpmos _i14 (_n17,1'b0,1'b0);
	and _i16 (_n19,_n12,PD);
	bufif1 _i17 (_n18,1'bx,_n19);
	nmos _i18 (_n15,_n17,_n16);
	pmos _i19 (_n15,_n18,_n16);
	nmos _i20 (_n10,_n14,_n11);
	pmos _i21 (_n10,_n15,_n11);
	nmos _i22 (_P,A,_n1);
	pmos _i23 (_P,_n10,_n1);
	nmos _i24 (P,_P,1'b1);
	or _i25 (_n22,SONOF,CONOF);
	and _i26 (D,P,_n22);
	specify
	
		(CONOF => D) = (0,0);
        (PEN => P) = (0,0,0,0,0,0);
        (PU => P) = (0,0,0,0,0,0);
        (PD => P) = (0,0,0,0,0,0);
        (SONOF => D) = (0,0);
	if(!CONOF&SONOF) (P => D) = (0,0);
	if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0);
	if(CONOF&!SONOF) (P => D) = (0,0);
	if(CONOF&SONOF) (P => D) = (0,0);
	if(NEN&!PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&!PD&PEN&PU) (A => P) = (0,0);
	if(NEN&PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&PD&PEN&PU) (A => P) = (0,0);
	ifnone (A => P) = (0,0,0,0,0,0);
	ifnone (NEN => P) = (0,0,0,0,0,0);
	ifnone (P => D) = (0,0);
	endspecify
endmodule
`endcelldefine
`celldefine
// 16 mA, slow slew rate, input-output pad, 5V tolerant
// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)
module PSBI16S (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF);
	output D;
	inout  P;
	input  A;
	input  CONOF;
	input  NEN;
	input  PD;
	input  PEN;
	input  PU;
	input  SONOF;
	wor P;
	not _i0 (_n3,PEN);
	not _i1 (_n4,NEN);
	and _i2 (_n2,_n3,_n4);
	and _i4 (_n5,A,_n3,NEN);
	not _i5 (_n8,A);
	and _i7 (_n7,_n8,PEN,_n4);
	nor _i8 (_n1,_n2,_n5,_n7);
	not _i9 (_n12,PU);
	not _i10 (_n13,PD);
	and _i11 (_n11,_n12,_n13);
	rnmos _i12 (_n14,1'b1,1'b1);
	and _i13 (_n16,PU,PD);
	rpmos _i14 (_n17,1'b0,1'b0);
	and _i16 (_n19,_n12,PD);
	bufif1 _i17 (_n18,1'bx,_n19);
	nmos _i18 (_n15,_n17,_n16);
	pmos _i19 (_n15,_n18,_n16);
	nmos _i20 (_n10,_n14,_n11);
	pmos _i21 (_n10,_n15,_n11);
	nmos _i22 (_P,A,_n1);
	pmos _i23 (_P,_n10,_n1);
	nmos _i24 (P,_P,1'b1);
	or _i25 (_n22,SONOF,CONOF);
	and _i26 (D,P,_n22);
	specify
	
		(CONOF => D) = (0,0);
        (PEN => P) = (0,0,0,0,0,0);
        (PU => P) = (0,0,0,0,0,0);
        (PD => P) = (0,0,0,0,0,0);
        (SONOF => D) = (0,0);
	if(!CONOF&SONOF) (P => D) = (0,0);
	if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0);
	if(CONOF&!SONOF) (P => D) = (0,0);
	if(CONOF&SONOF) (P => D) = (0,0);
	if(NEN&!PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&!PD&PEN&PU) (A => P) = (0,0);
	if(NEN&PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&PD&PEN&PU) (A => P) = (0,0);
	ifnone (A => P) = (0,0,0,0,0,0);
	ifnone (NEN => P) = (0,0,0,0,0,0);
	ifnone (P => D) = (0,0);
	endspecify
endmodule
`endcelldefine
`celldefine
// 24mA, fast slew rate, input-output pad, 5V tolerant
// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)
module PSBI24F (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF);
	output D;
	inout  P;
	input  A;
	input  CONOF;
	input  NEN;
	input  PD;
	input  PEN;
	input  PU;
	input  SONOF;
	wor P;
	not _i0 (_n3,PEN);
	not _i1 (_n4,NEN);
	and _i2 (_n2,_n3,_n4);
	and _i4 (_n5,A,_n3,NEN);
	not _i5 (_n8,A);
	and _i7 (_n7,_n8,PEN,_n4);
	nor _i8 (_n1,_n2,_n5,_n7);
	not _i9 (_n12,PU);
	not _i10 (_n13,PD);
	and _i11 (_n11,_n12,_n13);
	rnmos _i12 (_n14,1'b1,1'b1);
	and _i13 (_n16,PU,PD);
	rpmos _i14 (_n17,1'b0,1'b0);
	and _i16 (_n19,_n12,PD);
	bufif1 _i17 (_n18,1'bx,_n19);
	nmos _i18 (_n15,_n17,_n16);
	pmos _i19 (_n15,_n18,_n16);
	nmos _i20 (_n10,_n14,_n11);
	pmos _i21 (_n10,_n15,_n11);
	nmos _i22 (_P,A,_n1);
	pmos _i23 (_P,_n10,_n1);
	nmos _i24 (P,_P,1'b1);
	or _i25 (_n22,SONOF,CONOF);
	and _i26 (D,P,_n22);
	specify
	
		(CONOF => D) = (0,0);
        (PEN => P) = (0,0,0,0,0,0);
        (PU => P) = (0,0,0,0,0,0);
        (PD => P) = (0,0,0,0,0,0);
        (SONOF => D) = (0,0);
	if(!CONOF&SONOF) (P => D) = (0,0);
	if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0);
	if(CONOF&!SONOF) (P => D) = (0,0);
	if(CONOF&SONOF) (P => D) = (0,0);
	if(NEN&!PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&!PD&PEN&PU) (A => P) = (0,0);
	if(NEN&PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&PD&PEN&PU) (A => P) = (0,0);
	ifnone (A => P) = (0,0,0,0,0,0);
	ifnone (NEN => P) = (0,0,0,0,0,0);
	ifnone (P => D) = (0,0);
	endspecify
endmodule
`endcelldefine
`celldefine
// 24mA, normal slew rate, input-output pad, 5V tolerant
// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)
module PSBI24N (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF);
	output D;
	inout  P;
	input  A;
	input  CONOF;
	input  NEN;
	input  PD;
	input  PEN;
	input  PU;
	input  SONOF;
	wor P;
	not _i0 (_n3,PEN);
	not _i1 (_n4,NEN);
	and _i2 (_n2,_n3,_n4);
	and _i4 (_n5,A,_n3,NEN);
	not _i5 (_n8,A);
	and _i7 (_n7,_n8,PEN,_n4);
	nor _i8 (_n1,_n2,_n5,_n7);
	not _i9 (_n12,PU);
	not _i10 (_n13,PD);
	and _i11 (_n11,_n12,_n13);
	rnmos _i12 (_n14,1'b1,1'b1);
	and _i13 (_n16,PU,PD);
	rpmos _i14 (_n17,1'b0,1'b0);
	and _i16 (_n19,_n12,PD);
	bufif1 _i17 (_n18,1'bx,_n19);
	nmos _i18 (_n15,_n17,_n16);
	pmos _i19 (_n15,_n18,_n16);
	nmos _i20 (_n10,_n14,_n11);
	pmos _i21 (_n10,_n15,_n11);
	nmos _i22 (_P,A,_n1);
	pmos _i23 (_P,_n10,_n1);
	nmos _i24 (P,_P,1'b1);
	or _i25 (_n22,SONOF,CONOF);
	and _i26 (D,P,_n22);
	specify
	
		(CONOF => D) = (0,0);
        (PEN => P) = (0,0,0,0,0,0);
        (PU => P) = (0,0,0,0,0,0);
        (PD => P) = (0,0,0,0,0,0);
        (SONOF => D) = (0,0);
	if(!CONOF&SONOF) (P => D) = (0,0);
	if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0);
	if(CONOF&!SONOF) (P => D) = (0,0);
	if(CONOF&SONOF) (P => D) = (0,0);
	if(NEN&!PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&!PD&PEN&PU) (A => P) = (0,0);
	if(NEN&PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&PD&PEN&PU) (A => P) = (0,0);
	ifnone (A => P) = (0,0,0,0,0,0);
	ifnone (NEN => P) = (0,0,0,0,0,0);
	ifnone (P => D) = (0,0);
	endspecify
endmodule
`endcelldefine
`celldefine
// 24mA, slow slew rate, input-output pad, 5V tolerant
// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)
module PSBI24S (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF);
	output D;
	inout  P;
	input  A;
	input  CONOF;
	input  NEN;
	input  PD;
	input  PEN;
	input  PU;
	input  SONOF;
	wor P;
	not _i0 (_n3,PEN);
	not _i1 (_n4,NEN);
	and _i2 (_n2,_n3,_n4);
	and _i4 (_n5,A,_n3,NEN);
	not _i5 (_n8,A);
	and _i7 (_n7,_n8,PEN,_n4);
	nor _i8 (_n1,_n2,_n5,_n7);
	not _i9 (_n12,PU);
	not _i10 (_n13,PD);
	and _i11 (_n11,_n12,_n13);
	rnmos _i12 (_n14,1'b1,1'b1);
	and _i13 (_n16,PU,PD);
	rpmos _i14 (_n17,1'b0,1'b0);
	and _i16 (_n19,_n12,PD);
	bufif1 _i17 (_n18,1'bx,_n19);
	nmos _i18 (_n15,_n17,_n16);
	pmos _i19 (_n15,_n18,_n16);
	nmos _i20 (_n10,_n14,_n11);
	pmos _i21 (_n10,_n15,_n11);
	nmos _i22 (_P,A,_n1);
	pmos _i23 (_P,_n10,_n1);
	nmos _i24 (P,_P,1'b1);
	or _i25 (_n22,SONOF,CONOF);
	and _i26 (D,P,_n22);
	specify
	
		(CONOF => D) = (0,0);
        (PEN => P) = (0,0,0,0,0,0);
        (PU => P) = (0,0,0,0,0,0);
        (PD => P) = (0,0,0,0,0,0);
        (SONOF => D) = (0,0);
	if(!CONOF&SONOF) (P => D) = (0,0);
	if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0);
	if(CONOF&!SONOF) (P => D) = (0,0);
	if(CONOF&SONOF) (P => D) = (0,0);
	if(NEN&!PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&!PD&PEN&PU) (A => P) = (0,0);
	if(NEN&PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&PD&PEN&PU) (A => P) = (0,0);
	ifnone (A => P) = (0,0,0,0,0,0);
	ifnone (NEN => P) = (0,0,0,0,0,0);
	ifnone (P => D) = (0,0);
	endspecify
endmodule
`endcelldefine
`celldefine
// 2mA, fast slew rate, input-output pad, 5V tolerant
// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)
module PSBI2F (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF);
	output D;
	inout  P;
	input  A;
	input  CONOF;
	input  NEN;
	input  PD;
	input  PEN;
	input  PU;
	input  SONOF;
	wor P;
	not _i0 (_n3,PEN);
	not _i1 (_n4,NEN);
	and _i2 (_n2,_n3,_n4);
	and _i4 (_n5,A,_n3,NEN);
	not _i5 (_n8,A);
	and _i7 (_n7,_n8,PEN,_n4);
	nor _i8 (_n1,_n2,_n5,_n7);
	not _i9 (_n12,PU);
	not _i10 (_n13,PD);
	and _i11 (_n11,_n12,_n13);
	rnmos _i12 (_n14,1'b1,1'b1);
	and _i13 (_n16,PU,PD);
	rpmos _i14 (_n17,1'b0,1'b0);
	and _i16 (_n19,_n12,PD);
	bufif1 _i17 (_n18,1'bx,_n19);
	nmos _i18 (_n15,_n17,_n16);
	pmos _i19 (_n15,_n18,_n16);
	nmos _i20 (_n10,_n14,_n11);
	pmos _i21 (_n10,_n15,_n11);
	nmos _i22 (_P,A,_n1);
	pmos _i23 (_P,_n10,_n1);
	nmos _i24 (P,_P,1'b1);
	or _i25 (_n22,SONOF,CONOF);
	and _i26 (D,P,_n22);
	specify
	
		(CONOF => D) = (0,0);
        (PEN => P) = (0,0,0,0,0,0);
        (PU => P) = (0,0,0,0,0,0);
        (PD => P) = (0,0,0,0,0,0);
        (SONOF => D) = (0,0);
	if(!CONOF&SONOF) (P => D) = (0,0);
	if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0);
	if(CONOF&!SONOF) (P => D) = (0,0);
	if(CONOF&SONOF) (P => D) = (0,0);
	if(NEN&!PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&!PD&PEN&PU) (A => P) = (0,0);
	if(NEN&PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&PD&PEN&PU) (A => P) = (0,0);
	ifnone (A => P) = (0,0,0,0,0,0);
	ifnone (NEN => P) = (0,0,0,0,0,0);
	ifnone (P => D) = (0,0);
	endspecify
endmodule
`endcelldefine
`celldefine
// 2mA, normal slew rate, input-output pad, 5V tolerant
// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)
module PSBI2N (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF);
	output D;
	inout  P;
	input  A;
	input  CONOF;
	input  NEN;
	input  PD;
	input  PEN;
	input  PU;
	input  SONOF;
	wor P;
	not _i0 (_n3,PEN);
	not _i1 (_n4,NEN);
	and _i2 (_n2,_n3,_n4);
	and _i4 (_n5,A,_n3,NEN);
	not _i5 (_n8,A);
	and _i7 (_n7,_n8,PEN,_n4);
	nor _i8 (_n1,_n2,_n5,_n7);
	not _i9 (_n12,PU);
	not _i10 (_n13,PD);
	and _i11 (_n11,_n12,_n13);
	rnmos _i12 (_n14,1'b1,1'b1);
	and _i13 (_n16,PU,PD);
	rpmos _i14 (_n17,1'b0,1'b0);
	and _i16 (_n19,_n12,PD);
	bufif1 _i17 (_n18,1'bx,_n19);
	nmos _i18 (_n15,_n17,_n16);
	pmos _i19 (_n15,_n18,_n16);
	nmos _i20 (_n10,_n14,_n11);
	pmos _i21 (_n10,_n15,_n11);
	nmos _i22 (_P,A,_n1);
	pmos _i23 (_P,_n10,_n1);
	nmos _i24 (P,_P,1'b1);
	or _i25 (_n22,SONOF,CONOF);
	and _i26 (D,P,_n22);
	specify
	
		(CONOF => D) = (0,0);
        (PEN => P) = (0,0,0,0,0,0);
        (PU => P) = (0,0,0,0,0,0);
        (PD => P) = (0,0,0,0,0,0);
        (SONOF => D) = (0,0);
	if(!CONOF&SONOF) (P => D) = (0,0);
	if(!PD&!PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if(!PD&PEN&PU) (NEN => P) = (0,0,0,0,0,0);
	if((!NEN&!PD&PEN&PU|NEN&!PD&!PEN&PU)) (A => P) = (0,0);
	if(CONOF&!SONOF) (P => D) = (0,0);
	if(CONOF&SONOF) (P => D) = (0,0);
	if(NEN&!PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&!PD&PEN&PU) (A => P) = (0,0);
	if(NEN&PD&PEN&!PU) (A => P) = (0,0);
	if(NEN&PD&PEN&PU) (A => P) = (0,0);
	ifnone (A => P) = (0,0,0,0,0,0);
	ifnone (NEN => P) = (0,0,0,0,0,0);
	ifnone (P => D) = (0,0);
	endspecify
endmodule
`endcelldefine
`celldefine
// 2mA, slow slew rate, input-output pad, 5V tolerant
// P = PU&!PD&(!PEN&!NEN|!PEN&NEN&A|PEN&!NEN&!A) ? 'z' : PEN&NEN ? A : !PEN&NEN&!A ? 0 : PEN&!NEN&A ? 1 : (!PU&!PD ? 'h' : PU&PD ? 'l' : 'x');D = P&(SONOF|CONOF)
module PSBI2S (D, P, A, CONOF, NEN, PD, PEN, PU, SONOF);
	output D;
	inout  P;
	input  A;
	input  CONOF;
	input  NEN;
	input  PD;
	input  PEN;
	input  PU;
	input  SONOF;
	wor P;
	not _i0 (_n3,PEN);
	not _i1 (_n4,NEN);