📄 upsample.v
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`timescale 1ns/10ps
module upsample(data_in,clock,reset,data_out);
input [18:1] data_in;
input clock,reset;
output [18:1] data_out;
reg [18:1] data_out;
reg [3:1] times;
always@(posedge clock or negedge reset)
if(!reset)
begin
data_out=0;
times=0;
end
else
begin
if(!times)
begin
if(data_in)
begin
data_out=data_in;
times=times+1;
end
end
else
begin
data_out=0;
times=times+1;
if(times==3'b100)
times=0;
end
end
endmodule
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