top_half.v

插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现

`timescale 1ns/10ps
module top_half(data_in,clock_1,clock_2,reset,data_out);

input clock_1,clock_2,reset;
input [18:1] data_in;
output [18:1] data_out;

wire [18:1] buffer_out;
wire [18:1] dwire1,dwire2,dwire3,dwire4,dwire5,dwire6,dwire7,dwire8,dwire9,dwire10;
wire [18:1] dwire11,dwire12,dwire13,dwire14,dwire15,dwire16,dwire17,dwire18,dwire19,dwire20;
wire [18:1] dwire21,dwire22,dwire23,dwire24;
//wire [18:1] twire;

wire [19:1] div_in1,div_in2,div_in3,div_in4,div_in5,div_in6,div_in7,div_in8,div_in9,div_in10,div_in11,div_in12,div_in13;
wire [18:1] div_out1,div_out2,div_out3,div_out4,div_out5,div_out6,div_out7,div_out8,div_out9,div_out10,div_out11,div_out12,div_out13;

wire [19:1] minus_in1,minus_in2;

assign div_in13={1'b0,dwire12};

buffer buffer1(data_in,buffer_out);

FFD_hf_18_2 D2(buffer_out,clock_1,reset,dwire1),
            D4(dwire1,clock_1,reset,dwire2),
            D6(dwire2,clock_1,reset,dwire3),
            D8(dwire3,clock_1,reset,dwire4),
            D10(dwire4,clock_1,reset,dwire5),
            D12(dwire5,clock_1,reset,dwire6),
            D14(dwire6,clock_1,reset,dwire7),
            D16(dwire7,clock_1,reset,dwire8),
            D18(dwire8,clock_1,reset,dwire9),
            D20(dwire9,clock_1,reset,dwire10),
            D22(dwire10,clock_1,reset,dwire11);
         
FFD_hf_18   D23(dwire11,clock_1,reset,dwire12),
            D24(dwire12,clock_1,reset,dwire13);
                   
FFD_hf_18_2 D26(dwire13,clock_1,reset,dwire14),
            D28(dwire14,clock_1,reset,dwire15),
            D30(dwire15,clock_1,reset,dwire16),
            D32(dwire16,clock_1,reset,dwire17),
            D34(dwire17,clock_1,reset,dwire18),
            D36(dwire18,clock_1,reset,dwire19),
            D38(dwire19,clock_1,reset,dwire20),
            D40(dwire20,clock_1,reset,dwire21),
            D42(dwire21,clock_1,reset,dwire22),
            D44(dwire22,clock_1,reset,dwire23),
            D46(dwire23,clock_1,reset,dwire24);
         
add_half    add1(data_in,dwire24,div_in1),
            add2(dwire1,dwire23,div_in2),
            add3(dwire2,dwire22,div_in3),
            add4(dwire3,dwire21,div_in4),
            add5(dwire4,dwire20,div_in5),
            add6(dwire5,dwire19,div_in6),
            add7(dwire6,dwire18,div_in7),
            add8(dwire7,dwire17,div_in8),
            add9(dwire8,dwire16,div_in9),
            add10(dwire9,dwire15,div_in10),
            add11(dwire10,dwire14,div_in11),
            add12(dwire11,dwire13,div_in12);
         
hf_division1  hf_division1(div_in1,clock_1,reset,div_out1);
hf_division2  hf_division2(div_in2,clock_1,reset,div_out2);
hf_division3  hf_division3(div_in3,clock_1,reset,div_out3);
hf_division4  hf_division4(div_in4,clock_1,reset,div_out4);
hf_division5  hf_division5(div_in5,clock_1,reset,div_out5);
hf_division6  hf_division6(div_in6,clock_1,reset,div_out6);
hf_division7  hf_division7(div_in7,clock_1,reset,div_out7);
hf_division8  hf_division8(div_in8,clock_1,reset,div_out8);
hf_division9  hf_division9(div_in9,clock_1,reset,div_out9);
hf_division10 hf_division10(div_in10,clock_1,reset,div_out10);
hf_division11 hf_division11(div_in11,clock_1,reset,div_out11);
hf_division12 hf_division12(div_in12,clock_1,reset,div_out12);
hf_division13 hf_division13(div_in13,clock_1,reset,div_out13);
         
add_plus add_plus(div_out2,div_out4,div_out6,div_out8,div_out10,div_out12,div_out13,minus_in1);

add_negative add_negative(div_out1,div_out3,div_out5,div_out7,div_out9,div_out11,minus_in2); 

minus minus(minus_in1,minus_in2,data_out);

endmodule