📄 test_top_half.v
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`timescale 1ns/10ps
module test_top_half(data_out);
output [18:1] data_out;
wire [18:1] data_in;
wire clock,reset;
//wire [18:1] hf_out,multi_out;
integer fid;
top_total_sign top_total_sign(data_in,clock,reset);
top_half1 top_half1(data_in,clock,reset,data_out);
//top_half1 top_half1(data_in,clock1,reset,hf_out);
//top_multi1 top_multi1(hf_out,clock2,reset,multi_out);
//top_sh top_sh(multi_out,clock3,reset,data_out);
initial
begin
$monitor("%d %d %d",clock,data_in,data_out);
//fid = $fopen("e:/MATLAB6p5/work/total(10000).dat");
fid = $fopen("e:/total(10000).dat");
end
always @(posedge clock)
begin
if(clock)
begin
$fwrite(fid,"%d\n",data_out);
end
end
endmodule
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