hf_division12.v

来自「插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现」· Verilog 代码 · 共 32 行

`timescale 1ns/10ps
module hf_division12(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>2)+(temp_data>>4)+(temp_data>>8)+(temp_data>>11)+(temp_data>>12)+(temp_data>>17)+(temp_data>>18)+{~(temp_data>>15)+1};
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule           
         


//h22=0.317119776099350=0101,0001,0010,1110,11 change to csd 0101,0001,0011,00-10,11