📄 mux_2.v
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`timescale 1ns/10ps
module mux_2(data_in1,data_in2,control,data_out);
input [18:1] data_in1,data_in2;
input control;
output [18:1] data_out;
assign data_out = control ? data_in1 : data_in2;
endmodule
//module mux_3(data_in1,data_in2,control,data_out);
//input [18:1] data_in1,data_in2;
//input control;
//output [18:1] data_out;
//reg [18:1] data_out;
//always@(control)
//case(control)
// 1'b0 : data_out = data_in1;
// 1'b1 : data_out = data_in2;
// default : data_out = 0;
//endcase
//endmodule
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