mux_2.v

来自「插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现」· Verilog 代码 · 共 26 行

`timescale 1ns/10ps
module mux_2(data_in1,data_in2,control,data_out);

input [18:1] data_in1,data_in2;
input control;
output [18:1] data_out;

assign data_out = control ? data_in1 : data_in2;

endmodule

//module mux_3(data_in1,data_in2,control,data_out);

//input [18:1] data_in1,data_in2;
//input control;
//output [18:1] data_out;

//reg [18:1] data_out;

//always@(control)
//case(control)
//  1'b0 : data_out = data_in1;
//  1'b1 : data_out = data_in2;
//  default : data_out = 0;
//endcase  
//endmodule