top_multi.v

插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现

`timescale 1ns/10ps
module top_multi(data_in,clock,reset,data_out);

input [18:1] data_in;
input clock,reset;
output [18:1] data_out;

wire [18:1] buf_out;
wire [18:1] dwire1,dwire2,dwire3,dwire4,dwire5,dwire6,dwire7,dwire8,dwire9,dwire10;
wire [18:1] dwire11,dwire12,dwire13,dwire14,dwire15,dwire16,dwire17,dwire18,dwire19,dwire20,dwire21;

wire [19:1] div_in1,div_in2,div_in3,div_in4,div_in5,div_in6,div_in7,div_in8,div_in9,div_in10,div_in11;
wire [18:1] div_out1,div_out2,div_out3,div_out4,div_out5,div_out6,div_out7,div_out8,div_out9,div_out10,div_out11;

wire [19:1] minus_in1,minus_in2;

wire [18:1] shift_in;

assign div_in11={1'b0,dwire11};

buffer buffer2(data_in,buf_out);

upsample upsample(buf_out,clock,reset,dwire1);

FFD_lp_18 FFD1(dwire1,clock,reset,dwire2),
          FFD2(dwire2,clock,reset,dwire3),
          FFD3(dwire3,clock,reset,dwire4),
          FFD4(dwire4,clock,reset,dwire5),
          FFD5(dwire5,clock,reset,dwire6),
          FFD6(dwire6,clock,reset,dwire7),
          FFD7(dwire7,clock,reset,dwire8),
          FFD8(dwire8,clock,reset,dwire9),
          FFD9(dwire9,clock,reset,dwire10),
          FFD10(dwire10,clock,reset,dwire11),
          FFD11(dwire11,clock,reset,dwire12),
          FFD12(dwire12,clock,reset,dwire13),
          FFD13(dwire13,clock,reset,dwire14),
          FFD14(dwire14,clock,reset,dwire15),
          FFD15(dwire15,clock,reset,dwire16),
          FFD16(dwire16,clock,reset,dwire17),
          FFD17(dwire17,clock,reset,dwire18),
          FFD18(dwire18,clock,reset,dwire19),
          FFD19(dwire19,clock,reset,dwire20),
          FFD20(dwire20,clock,reset,dwire21);
       
add_multi    add1(dwire1,dwire21,div_in1),
             add2(dwire2,dwire20,div_in2),
             add3(dwire3,dwire19,div_in3),
             add4(dwire4,dwire18,div_in4),
             add5(dwire5,dwire17,div_in5),
             add6(dwire6,dwire16,div_in6),
             add7(dwire7,dwire15,div_in7),
             add8(dwire8,dwire14,div_in8),
             add9(dwire9,dwire13,div_in9),
             add10(dwire10,dwire12,div_in10);
         
lp_division1 lp_division1(div_in1,clock,reset,div_out1);
lp_division2 lp_division2(div_in2,clock,reset,div_out2);
lp_division3 lp_division3(div_in3,clock,reset,div_out3);
lp_division4 lp_division4(div_in4,clock,reset,div_out4);
lp_division5 lp_division5(div_in5,clock,reset,div_out5);
lp_division6 lp_division6(div_in6,clock,reset,div_out6);
lp_division7 lp_division7(div_in7,clock,reset,div_out7);
lp_division8 lp_division8(div_in8,clock,reset,div_out8);
lp_division9 lp_division9(div_in9,clock,reset,div_out9);
lp_division10 lp_division10(div_in10,clock,reset,div_out10);
lp_division11 lp_division11(div_in11,clock,reset,div_out11);                

add_z add_z(div_out3,div_out4,div_out5,div_out9,div_out10,div_out11,minus_in1);

add_f add_f(div_out1,div_out2,div_out6,div_out7,div_out8,minus_in2); 

minus minus(minus_in1,minus_in2,shift_in);

shift_up shift_up(shift_in,data_out);


endmodule