top_core.v

来自「插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现」· Verilog 代码 · 共 21 行

`timescale 1ns/10ps
module top_core(data_in,clock,reset,control,data_out);

input [18:1] data_in;
input clock,reset;
input [4:1] control;
output [18:1] data_out;

wire [18:1] hf_out,multi_out,sh_out,mux1_out,mux2_out;
wire clock_hf_1,clock_hf_2,clock_lp,clock_sh;

clk_divide clk_divide(clock,reset,clock_hf_1,clock_hf_2,clock_lp,clock_sh);
top_half top_half(data_in,clock_hf_1,clock_hf_2,reset,hf_out);
mux_2 mux1(hf_out,data_in,control[1],mux1_out);
top_multi top_multi(mux1_out,clock_lp,reset,multi_out);
mux_2 mux2(multi_out,data_in,control[2],mux2_out);
top_sh top_sh(mux2_out,clock_sh,reset,sh_out);
mux_4 mux3(data_in,mux1_out,mux2_out,sh_out,control[4:3],data_out);


endmodule