ffd_18_2.v

来自「插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现」· Verilog 代码 · 共 14 行

`timescale 1ns/10ps
module FFD_18_2(data,clock,reset,q);

input [18:1] data;
input clock,reset;
output [18:1] q;

wire [18:1] connect;

FFD_18 FFD1(data,clock,reset,connect),
       FFD2(connect,clock,reset,q);

endmodule