ffd_lp.v

来自「插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现」· Verilog 代码 · 共 12 行

`timescale 1ns/10ps
module FFD_lp(data,clock,reset,q);
output q;
input  data,clock,reset;
reg q;
always@(negedge clock or negedge reset)
    if(~reset)
       q<=0;
    else
       q<=data;     
endmodule