shift_up.v

来自「插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现」· Verilog 代码 · 共 10 行

`timescale 1ns/10ps
module shift_up(data_in,data_out);

input [18:1] data_in;
output [18:1] data_out;

assign data_out=data_in<<2;

endmodule