smic18.v

插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现

   and (I0_out, A, B);
   and (I1_out, I0_out, C);
   and (I2_out, D, E);
   or  (I3_out, I1_out, I2_out);
   not (Z, I3_out);
   not (I5_out, D);
   not (I6_out, E);
   and (I7_out, I5_out, I6_out);
   not (I8_out, E);
   and (I9_out, D, I8_out);
   or  (\!D&!E|D&!E , I7_out, I9_out);
   not (I11_out, D);
   and (\!D&E , I11_out, E);
   not (I13_out, E);
   and (I14_out, D, I13_out);
   not (I15_out, D);
   not (I16_out, E);
   and (I17_out, I15_out, I16_out);
   or  (\D&!E|!D&!E , I14_out, I17_out);
   not (I19_out, A);
   not (I20_out, B);
   and (I21_out, I19_out, I20_out);
   not (I22_out, C);
   and (I23_out, I21_out, I22_out);
   and (I24_out, A, B);
   not (I25_out, C);
   and (I26_out, I24_out, I25_out);
   or  (\!A&!B&!C|A&B&!C , I23_out, I26_out);
   not (I28_out, B);
   and (I29_out, A, I28_out);
   and (I30_out, I29_out, C);
   not (I31_out, A);
   and (I32_out, I31_out, B);
   and (I33_out, I32_out, C);
   or  (\A&!B&C|!A&B&C , I30_out, I33_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!D&!E|D&!E )
       (A *> Z) = (0, 0);
     if (!D&E )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!D&!E|D&!E )
       (B *> Z) = (0, 0);
     if (!D&E )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!D&E )
       (C *> Z) = (0, 0);
     if (D&!E|!D&!E )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (E *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (E *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI32HD2X (A, B, C, D, E, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
output Z ;

   and (I0_out, D, E);
   and (I1_out, A, B);
   and (I2_out, I1_out, C);
   or  (I3_out, I0_out, I2_out);
   not (Z, I3_out);
   not (I5_out, D);
   not (I6_out, E);
   and (I7_out, I5_out, I6_out);
   not (I8_out, E);
   and (I9_out, D, I8_out);
   or  (\!D&!E|D&!E , I7_out, I9_out);
   not (I11_out, D);
   and (\!D&E , I11_out, E);
   not (I13_out, E);
   and (I14_out, D, I13_out);
   not (I15_out, D);
   not (I16_out, E);
   and (I17_out, I15_out, I16_out);
   or  (\D&!E|!D&!E , I14_out, I17_out);
   not (I19_out, A);
   not (I20_out, B);
   and (I21_out, I19_out, I20_out);
   not (I22_out, C);
   and (I23_out, I21_out, I22_out);
   and (I24_out, A, B);
   not (I25_out, C);
   and (I26_out, I24_out, I25_out);
   or  (\!A&!B&!C|A&B&!C , I23_out, I26_out);
   not (I28_out, B);
   and (I29_out, A, I28_out);
   and (I30_out, I29_out, C);
   not (I31_out, A);
   and (I32_out, I31_out, B);
   and (I33_out, I32_out, C);
   or  (\A&!B&C|!A&B&C , I30_out, I33_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!D&!E|D&!E )
       (A *> Z) = (0, 0);
     if (!D&E )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!D&!E|D&!E )
       (B *> Z) = (0, 0);
     if (!D&E )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!D&E )
       (C *> Z) = (0, 0);
     if (D&!E|!D&!E )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (E *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (E *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI32HD4X (A, B, C, D, E, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
output Z ;

   and (I0_out, D, E);
   and (I1_out, A, B);
   and (I2_out, I1_out, C);
   or  (I3_out, I0_out, I2_out);
   not (Z, I3_out);
   not (I5_out, D);
   not (I6_out, E);
   and (I7_out, I5_out, I6_out);
   not (I8_out, E);
   and (I9_out, D, I8_out);
   or  (\!D&!E|D&!E , I7_out, I9_out);
   not (I11_out, D);
   and (\!D&E , I11_out, E);
   not (I13_out, A);
   not (I14_out, B);
   and (I15_out, I13_out, I14_out);
   not (I16_out, C);
   and (I17_out, I15_out, I16_out);
   and (I18_out, A, B);
   not (I19_out, C);
   and (I20_out, I18_out, I19_out);
   or  (\!A&!B&!C|A&B&!C , I17_out, I20_out);
   not (I22_out, B);
   and (I23_out, A, I22_out);
   and (I24_out, I23_out, C);
   not (I25_out, A);
   and (I26_out, I25_out, B);
   and (I27_out, I26_out, C);
   or  (\A&!B&C|!A&B&C , I24_out, I27_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!D&!E|D&!E )
       (A *> Z) = (0, 0);
     if (!D&E )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!D&!E|D&!E )
       (B *> Z) = (0, 0);
     if (!D&E )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!D&!E|D&!E )
       (C *> Z) = (0, 0);
     if (!D&E )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (E *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (E *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI32HDLX (A, B, C, D, E, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
output Z ;

   and (I0_out, D, E);
   and (I1_out, A, B);
   and (I2_out, I1_out, C);
   or  (I3_out, I0_out, I2_out);
   not (Z, I3_out);
   not (I5_out, D);
   not (I6_out, E);
   and (I7_out, I5_out, I6_out);
   not (I8_out, E);
   and (I9_out, D, I8_out);
   or  (\!D&!E|D&!E , I7_out, I9_out);
   not (I11_out, D);
   and (\!D&E , I11_out, E);
   not (I13_out, A);
   not (I14_out, B);
   and (I15_out, I13_out, I14_out);
   not (I16_out, C);
   and (I17_out, I15_out, I16_out);
   and (I18_out, A, B);
   not (I19_out, C);
   and (I20_out, I18_out, I19_out);
   or  (\!A&!B&!C|A&B&!C , I17_out, I20_out);
   not (I22_out, B);
   and (I23_out, A, I22_out);
   and (I24_out, I23_out, C);
   not (I25_out, A);
   and (I26_out, I25_out, B);
   and (I27_out, I26_out, C);
   or  (\A&!B&C|!A&B&C , I24_out, I27_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!D&!E|D&!E )
       (A *> Z) = (0, 0);
     if (!D&E )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!D&!E|D&!E )
       (B *> Z) = (0, 0);
     if (!D&E )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!D&!E|D&!E )
       (C *> Z) = (0, 0);
     if (!D&E )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (E *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (E *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI33HD1X (A, B, C, D, E, F, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
input  F ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, I0_out, C);
   and (I2_out, D, E);
   and (I3_out, I2_out, F);
   or  (I4_out, I1_out, I3_out);
   not (Z, I4_out);
   not (I6_out, D);
   not (I7_out, E);
   and (I8_out, I6_out, I7_out);
   not (I9_out, F);
   and (I10_out, I8_out, I9_out);
   and (I11_out, D, E);
   not (I12_out, F);
   and (I13_out, I11_out, I12_out);
   or  (\!D&!E&!F|D&E&!F , I10_out, I13_out);
   not (I15_out, E);
   and (I16_out, D, I15_out);
   and (I17_out, I16_out, F);
   not (I18_out, D);
   and (I19_out, I18_out, E);
   and (I20_out, I19_out, F);
   or  (\D&!E&F|!D&E&F , I17_out, I20_out);
   and (I22_out, D, E);
   not (I23_out, F);
   and (I24_out, I22_out, I23_out);
   not (I25_out, D);
   not (I26_out, E);
   and (I27_out, I25_out, I26_out);
   not (I28_out, F);
   and (I29_out, I27_out, I28_out);
   or  (\D&E&!F|!D&!E&!F , I24_out, I29_out);
   not (I31_out, A);
   not (I32_out, B);
   and (I33_out, I31_out, I32_out);
   not (I34_out, C);
   and (I35_out, I33_out, I34_out);
   and (I36_out, A, B);
   not (I37_out, C);
   and (I38_out, I36_out, I37_out);
   or  (\!A&!B&!C|A&B&!C , I35_out, I38_out);
   not (I40_out, B);
   and (I41_out, A, I40_out);
   and (I42_out, I41_out, C);
   not (I43_out, A);
   and (I44_out, I43_out, B);
   and (I45_out, I44_out, C);
   or  (\A&!B&C|!A&B&C , I42_out, I45_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!D&!E&!F|D&E&!F )
       (A *> Z) = (0, 0);
     if (D&!E&F|!D&E&F )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!D&!E&!F|D&E&!F )
       (B *> Z) = (0, 0);
     if (D&!E&F|!D&E&F )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (D&!E&F|!D&E&F )
       (C *> Z) = (0, 0);
     if (D&E&!F|!D&!E&!F )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (E *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (E *> Z) = (0, 0);
     ifnone (F *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (F *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (F *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI33HD2X (A, B, C, D, E, F, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
input  F ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, I0_out, C);
   and (I2_out, D, E);
   and (I3_out, I2_out, F);
   or  (I4_out, I1_out, I3_out);
   not (Z, I4_out);
   not (I6_out, D);
   not (I7_out, E);
   and (I8_out, I6_out, I7_out);
   not (I9_out, F);
   and (I10_out, I8_out, I9_out);
   and (I11_out, D, E);
   not (I12_out, F);
   and (I13_out, I11_out, I12_out);
   or  (\!D&!E&!F|D&E&!F , I10_out, I13_out);
   not (I15_out, E);
   and (I16_out, D, I15_out);
   and (I17_out, I16_out, F);
   not (I18_out, D);
   and (I19_out, I18_out, E);
   and (I20_out, I19_out, F);
   or  (\D&!E&F|!D&E&F , I17_out, I20_out);
   and (I22_out, D, E);
   not (I23_out, F);
   and (I24_out, I22_out, I23_out);
   not (I25_out, D);
   not (I26_out, E);
   and (I27_out, I25_out, I26_out);
   not (I28_out, F);
   and (I29_out, I27_out, I28_out);
   or  (\D&E&!F|!D&!E&!F , I24_out, I29_out);
   not (I31_out, A);
   not (I32_out, B);
   and (I33_out, I31_out, I32_out);
   not (I34_out, C);
   and (I35_out, I33_out, I34_out);
   and (I36_out, A, B);
   not (I37_out, C);
   and (I38_out, I36_out, I37_out);
   or  (\!A&!B&!C|A&B&!C , I35_out, I38_out);
   not (I40_out, B);
   and (I41_out, A, I40_out);
   and (I42_out, I41_out, C);
   not (I43_out, A);
   and (I44_out, I43_out, B);
   and (I45_out, I44_out, C);
   or  (\A&!B&C|!A&B&C , I42_out, I45_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!D&!E&!F|D&E&!F )
       (A *> Z) = (0, 0);
     if (D&!E&F|!D&E&F )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!D&!E&!F|D&E&!F )
       (B *> Z) = (0, 0);
     if (D&!E&F|!D&E&F )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (D&!E&F|!D&E&F )
       (C *> Z) = (0, 0);
     if (D&E&!F|!D&!E&!F )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (E *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (E *> Z) = (0, 0);
     ifnone (F *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (F *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (F *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI33HD4X (A, B, C, D, E, F, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
input  F ;
output Z ;

   and (I0_out, D, E);
   and (I1_out, I0_out, F);
   and (I2_out, A, B);
   and (I3_out, I2_out, C);
   or  (I4_out, I1_out, I3_out);
   not (Z, I4_out);
   not (I6_out, D);
   not (I7_out, E);
   and (I8_out, I6_out, I7_out);
   not (I9_out, F);
   and (I10_out, I8_out, I9_out);
   and (I11_out, D, E);
   not (I12_out, F);
   and (I13_out, I11_out, I12_out);
   or  (\!D&!E&!F|D&E&!F , I10_out, I13_out);
   not (I15_out, E);
   and (I16_out, D, I15_out);
   and (I17_out, I16_out, F);
   not (I18_out, D);
   and (I19_out, I18_out, E);
   and (I20_out, I19_out, F);
   or  (\D&!E&F|!D&E&F , I17_out, I20_out);
   not (I22_out, A);
   not (I23_out, B);
   and (I24_out, I22_out, I23_out);
   not (I25_out, C);
   and (I26_out, I24_out, I25_out);
   and (I27_out, A, B);
   not (I28_out, C);
   and (I29_out, I27_out, I28_out);
   or  (\!A&!B&!C|A&B&!C , I26_out, I29_out);
   not (I31_out, B);
   and (I32_out, A, I31_out);
   and (I33_out, I32_out, C);
   not (I34_out, A);
   and (I35_out, I34_out, B);
   and (I36_out, I35_out, C);
   or  (\A&!B&C|!A&B&C , I33_out, I36_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!D&!E&!F|D&E&!F )
       (A *> Z) = (0, 0);
     if (D&!E&F|!D&E&F )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!D&!E&!F|D&E&!F )
       (B *> Z) = (0, 0);
     if (D&!E&F|!D&E&F )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!D&!E&!F|D&E&!F )
       (C *> Z) = (0, 0);
     if (D&!E&F|!D&E&F )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (E *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (E *> Z) = (0, 0);
     ifnone (F *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (F *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (F *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI33HDLX (A, B, C, D, E, F, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
input  F ;
output Z ;

   and (I0_out, D, E);
   and (I1_out, I0_out, F);
   and (I2_out, A, B);
   and (I3_out, I2_out, C);
   or  (I4_out, I1_out, I3_out);
   not (Z, I4_out);