smic18.v

插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现

   or  (I1_out, AN, BN);
   not (I2_out, I1_out);
   or  (I3_out, I0_out, I2_out);
   not (Z, I3_out);
   not (I5_out, C);
   not (I6_out, D);
   and (I7_out, I5_out, I6_out);
   not (I8_out, D);
   and (I9_out, C, I8_out);
   or  (\!C&!D|C&!D , I7_out, I9_out);
   not (I11_out, C);
   and (\!C&D , I11_out, D);

   specify
     // path delays
     ifnone (AN *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (AN *> Z) = (0, 0);
     if (!C&D )
       (AN *> Z) = (0, 0);
     ifnone (BN *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (BN *> Z) = (0, 0);
     if (!C&D )
       (BN *> Z) = (0, 0);
     (C *> Z) = (0, 0);
     (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI22B2HD2X (AN, BN, C, D, Z);
input  AN ;
input  BN ;
input  C ;
input  D ;
output Z ;

   and (I0_out, C, D);
   or  (I1_out, AN, BN);
   not (I2_out, I1_out);
   or  (I3_out, I0_out, I2_out);
   not (Z, I3_out);
   not (I5_out, C);
   not (I6_out, D);
   and (I7_out, I5_out, I6_out);
   not (I8_out, D);
   and (I9_out, C, I8_out);
   or  (\!C&!D|C&!D , I7_out, I9_out);
   not (I11_out, C);
   and (\!C&D , I11_out, D);

   specify
     // path delays
     ifnone (AN *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (AN *> Z) = (0, 0);
     if (!C&D )
       (AN *> Z) = (0, 0);
     ifnone (BN *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (BN *> Z) = (0, 0);
     if (!C&D )
       (BN *> Z) = (0, 0);
     (C *> Z) = (0, 0);
     (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI22B2HD4X (AN, BN, C, D, Z);
input  AN ;
input  BN ;
input  C ;
input  D ;
output Z ;

   and (I0_out, C, D);
   or  (I1_out, AN, BN);
   not (I2_out, I1_out);
   or  (I3_out, I0_out, I2_out);
   not (Z, I3_out);
   not (I5_out, C);
   not (I6_out, D);
   and (I7_out, I5_out, I6_out);
   not (I8_out, D);
   and (I9_out, C, I8_out);
   or  (\!C&!D|C&!D , I7_out, I9_out);
   not (I11_out, C);
   and (\!C&D , I11_out, D);

   specify
     // path delays
     ifnone (AN *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (AN *> Z) = (0, 0);
     if (!C&D )
       (AN *> Z) = (0, 0);
     ifnone (BN *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (BN *> Z) = (0, 0);
     if (!C&D )
       (BN *> Z) = (0, 0);
     (C *> Z) = (0, 0);
     (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI22B2HDLX (AN, BN, C, D, Z);
input  AN ;
input  BN ;
input  C ;
input  D ;
output Z ;

   and (I0_out, C, D);
   or  (I1_out, AN, BN);
   not (I2_out, I1_out);
   or  (I3_out, I0_out, I2_out);
   not (Z, I3_out);
   not (I5_out, C);
   not (I6_out, D);
   and (I7_out, I5_out, I6_out);
   not (I8_out, D);
   and (I9_out, C, I8_out);
   or  (\!C&!D|C&!D , I7_out, I9_out);
   not (I11_out, C);
   and (\!C&D , I11_out, D);

   specify
     // path delays
     ifnone (AN *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (AN *> Z) = (0, 0);
     if (!C&D )
       (AN *> Z) = (0, 0);
     ifnone (BN *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (BN *> Z) = (0, 0);
     if (!C&D )
       (BN *> Z) = (0, 0);
     (C *> Z) = (0, 0);
     (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI22HD1X (A, B, C, D, Z);
input  A ;
input  B ;
input  C ;
input  D ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, C, D);
   or  (I2_out, I0_out, I1_out);
   not (Z, I2_out);
   not (I4_out, C);
   not (I5_out, D);
   and (I6_out, I4_out, I5_out);
   not (I7_out, C);
   and (I8_out, I7_out, D);
   or  (\!C&!D|!C&D , I6_out, I8_out);
   not (I10_out, D);
   and (\C&!D , C, I10_out);
   not (I12_out, C);
   and (I13_out, I12_out, D);
   not (I14_out, C);
   not (I15_out, D);
   and (I16_out, I14_out, I15_out);
   or  (\!C&D|!C&!D , I13_out, I16_out);
   not (I18_out, A);
   not (I19_out, B);
   and (I20_out, I18_out, I19_out);
   not (I21_out, B);
   and (I22_out, A, I21_out);
   or  (\!A&!B|A&!B , I20_out, I22_out);
   not (I24_out, A);
   and (\!A&B , I24_out, B);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!C&!D|!C&D )
       (A *> Z) = (0, 0);
     if (C&!D )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!C&D|!C&!D )
       (B *> Z) = (0, 0);
     if (C&!D )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (D *> Z) = (0, 0);
     if (!A&B )
       (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI22HD2X (A, B, C, D, Z);
input  A ;
input  B ;
input  C ;
input  D ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, C, D);
   or  (I2_out, I0_out, I1_out);
   not (Z, I2_out);
   not (I4_out, C);
   not (I5_out, D);
   and (I6_out, I4_out, I5_out);
   not (I7_out, C);
   and (I8_out, I7_out, D);
   or  (\!C&!D|!C&D , I6_out, I8_out);
   not (I10_out, D);
   and (\C&!D , C, I10_out);
   not (I12_out, A);
   not (I13_out, B);
   and (I14_out, I12_out, I13_out);
   not (I15_out, B);
   and (I16_out, A, I15_out);
   or  (\!A&!B|A&!B , I14_out, I16_out);
   not (I18_out, A);
   and (\!A&B , I18_out, B);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!C&!D|!C&D )
       (A *> Z) = (0, 0);
     if (C&!D )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!C&!D|!C&D )
       (B *> Z) = (0, 0);
     if (C&!D )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (D *> Z) = (0, 0);
     if (!A&B )
       (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI22HD4X (A, B, C, D, Z);
input  A ;
input  B ;
input  C ;
input  D ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, C, D);
   or  (I2_out, I0_out, I1_out);
   not (Z, I2_out);
   not (I4_out, C);
   not (I5_out, D);
   and (I6_out, I4_out, I5_out);
   not (I7_out, C);
   and (I8_out, I7_out, D);
   or  (\!C&!D|!C&D , I6_out, I8_out);
   not (I10_out, D);
   and (\C&!D , C, I10_out);
   not (I12_out, A);
   not (I13_out, B);
   and (I14_out, I12_out, I13_out);
   not (I15_out, B);
   and (I16_out, A, I15_out);
   or  (\!A&!B|A&!B , I14_out, I16_out);
   not (I18_out, A);
   and (\!A&B , I18_out, B);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!C&!D|!C&D )
       (A *> Z) = (0, 0);
     if (C&!D )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!C&!D|!C&D )
       (B *> Z) = (0, 0);
     if (C&!D )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (D *> Z) = (0, 0);
     if (!A&B )
       (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI22HDLX (A, B, C, D, Z);
input  A ;
input  B ;
input  C ;
input  D ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, C, D);
   or  (I2_out, I0_out, I1_out);
   not (Z, I2_out);
   not (I4_out, C);
   not (I5_out, D);
   and (I6_out, I4_out, I5_out);
   not (I7_out, C);
   and (I8_out, I7_out, D);
   or  (\!C&!D|!C&D , I6_out, I8_out);
   not (I10_out, D);
   and (\C&!D , C, I10_out);
   not (I12_out, A);
   not (I13_out, B);
   and (I14_out, I12_out, I13_out);
   not (I15_out, B);
   and (I16_out, A, I15_out);
   or  (\!A&!B|A&!B , I14_out, I16_out);
   not (I18_out, A);
   and (\!A&B , I18_out, B);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!C&!D|!C&D )
       (A *> Z) = (0, 0);
     if (C&!D )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!C&!D|!C&D )
       (B *> Z) = (0, 0);
     if (C&!D )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (D *> Z) = (0, 0);
     if (!A&B )
       (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI31HD1X (A, B, C, D, Z);
input  A ;
input  B ;
input  C ;
input  D ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, I0_out, C);
   or  (I2_out, I1_out, D);
   not (Z, I2_out);
   not (I4_out, A);
   not (I5_out, B);
   and (I6_out, I4_out, I5_out);
   not (I7_out, C);
   and (I8_out, I6_out, I7_out);
   and (I9_out, A, B);
   not (I10_out, C);
   and (I11_out, I9_out, I10_out);
   or  (\!A&!B&!C|A&B&!C , I8_out, I11_out);
   not (I13_out, B);
   and (I14_out, A, I13_out);
   and (I15_out, I14_out, C);
   not (I16_out, A);
   and (I17_out, I16_out, B);
   and (I18_out, I17_out, C);
   or  (\A&!B&C|!A&B&C , I15_out, I18_out);

   specify
     // path delays
     (A *> Z) = (0, 0);
     (B *> Z) = (0, 0);
     (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI31HD2X (A, B, C, D, Z);
input  A ;
input  B ;
input  C ;
input  D ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, I0_out, C);
   or  (I2_out, I1_out, D);
   not (Z, I2_out);
   not (I4_out, A);
   not (I5_out, B);
   and (I6_out, I4_out, I5_out);
   not (I7_out, C);
   and (I8_out, I6_out, I7_out);
   and (I9_out, A, B);
   not (I10_out, C);
   and (I11_out, I9_out, I10_out);
   or  (\!A&!B&!C|A&B&!C , I8_out, I11_out);
   not (I13_out, B);
   and (I14_out, A, I13_out);
   and (I15_out, I14_out, C);
   not (I16_out, A);
   and (I17_out, I16_out, B);
   and (I18_out, I17_out, C);
   or  (\A&!B&C|!A&B&C , I15_out, I18_out);

   specify
     // path delays
     (A *> Z) = (0, 0);
     (B *> Z) = (0, 0);
     (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI31HD4X (A, B, C, D, Z);
input  A ;
input  B ;
input  C ;
input  D ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, I0_out, C);
   or  (I2_out, I1_out, D);
   not (Z, I2_out);
   not (I4_out, A);
   not (I5_out, B);
   and (I6_out, I4_out, I5_out);
   not (I7_out, C);
   and (I8_out, I6_out, I7_out);
   and (I9_out, A, B);
   not (I10_out, C);
   and (I11_out, I9_out, I10_out);
   or  (\!A&!B&!C|A&B&!C , I8_out, I11_out);
   not (I13_out, B);
   and (I14_out, A, I13_out);
   and (I15_out, I14_out, C);
   not (I16_out, A);
   and (I17_out, I16_out, B);
   and (I18_out, I17_out, C);
   or  (\A&!B&C|!A&B&C , I15_out, I18_out);

   specify
     // path delays
     (A *> Z) = (0, 0);
     (B *> Z) = (0, 0);
     (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI31HDLX (A, B, C, D, Z);
input  A ;
input  B ;
input  C ;
input  D ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, I0_out, C);
   or  (I2_out, I1_out, D);
   not (Z, I2_out);
   not (I4_out, A);
   not (I5_out, B);
   and (I6_out, I4_out, I5_out);
   not (I7_out, C);
   and (I8_out, I6_out, I7_out);
   and (I9_out, A, B);
   not (I10_out, C);
   and (I11_out, I9_out, I10_out);
   or  (\!A&!B&!C|A&B&!C , I8_out, I11_out);
   not (I13_out, B);
   and (I14_out, A, I13_out);
   and (I15_out, I14_out, C);
   not (I16_out, A);
   and (I17_out, I16_out, B);
   and (I18_out, I17_out, C);
   or  (\A&!B&C|!A&B&C , I15_out, I18_out);

   specify
     // path delays
     (A *> Z) = (0, 0);
     (B *> Z) = (0, 0);
     (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B&!C|A&B&!C )
       (D *> Z) = (0, 0);
     if (A&!B&C|!A&B&C )
       (D *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI32HD1X (A, B, C, D, E, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
output Z ;