smic18.v

插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现

       (C *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI21HD2X (A, B, C, Z);
input  A ;
input  B ;
input  C ;
output Z ;

   and (I0_out, A, B);
   or  (I1_out, I0_out, C);
   not (Z, I1_out);
   not (I3_out, A);
   not (I4_out, B);
   and (I5_out, I3_out, I4_out);
   not (I6_out, B);
   and (I7_out, A, I6_out);
   or  (\!A&!B|A&!B , I5_out, I7_out);
   not (I9_out, A);
   and (\!A&B , I9_out, B);

   specify
     // path delays
     (A *> Z) = (0, 0);
     (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI21HD4X (A, B, C, Z);
input  A ;
input  B ;
input  C ;
output Z ;

   and (I0_out, A, B);
   or  (I1_out, I0_out, C);
   not (Z, I1_out);
   not (I3_out, A);
   not (I4_out, B);
   and (I5_out, I3_out, I4_out);
   not (I6_out, B);
   and (I7_out, A, I6_out);
   or  (\!A&!B|A&!B , I5_out, I7_out);
   not (I9_out, A);
   and (\!A&B , I9_out, B);

   specify
     // path delays
     (A *> Z) = (0, 0);
     (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI21HDLX (A, B, C, Z);
input  A ;
input  B ;
input  C ;
output Z ;

   and (I0_out, A, B);
   or  (I1_out, I0_out, C);
   not (Z, I1_out);
   not (I3_out, A);
   not (I4_out, B);
   and (I5_out, I3_out, I4_out);
   not (I6_out, B);
   and (I7_out, A, I6_out);
   or  (\!A&!B|A&!B , I5_out, I7_out);
   not (I9_out, A);
   and (\!A&B , I9_out, B);

   specify
     // path delays
     (A *> Z) = (0, 0);
     (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI221HD1X (A, B, C, D, E, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, C, D);
   or  (I2_out, I0_out, I1_out);
   or  (I3_out, I2_out, E);
   not (Z, I3_out);
   not (I5_out, C);
   not (I6_out, D);
   and (I7_out, I5_out, I6_out);
   not (I8_out, D);
   and (I9_out, C, I8_out);
   or  (\!C&!D|C&!D , I7_out, I9_out);
   not (I11_out, C);
   and (\!C&D , I11_out, D);
   not (I13_out, A);
   not (I14_out, B);
   and (I15_out, I13_out, I14_out);
   not (I16_out, B);
   and (I17_out, A, I16_out);
   or  (\!A&!B|A&!B , I15_out, I17_out);
   not (I19_out, A);
   and (\!A&B , I19_out, B);
   not (I21_out, A);
   not (I22_out, B);
   and (I23_out, I21_out, I22_out);
   not (I24_out, C);
   and (I25_out, I23_out, I24_out);
   not (I26_out, D);
   and (I27_out, I25_out, I26_out);
   not (I28_out, B);
   and (I29_out, A, I28_out);
   and (I30_out, I29_out, C);
   not (I31_out, D);
   and (I32_out, I30_out, I31_out);
   or  (\!A&!B&!C&!D|A&!B&C&!D , I27_out, I32_out);
   not (I34_out, B);
   and (I35_out, A, I34_out);
   not (I36_out, C);
   and (I37_out, I35_out, I36_out);
   and (I38_out, I37_out, D);
   not (I39_out, A);
   and (I40_out, I39_out, B);
   and (I41_out, I40_out, C);
   not (I42_out, D);
   and (I43_out, I41_out, I42_out);
   or  (I44_out, I38_out, I43_out);
   not (I45_out, A);
   and (I46_out, I45_out, B);
   not (I47_out, C);
   and (I48_out, I46_out, I47_out);
   and (I49_out, I48_out, D);
   or  (\A&!B&!C&D|!A&B&C&!D|!A&B&!C&D , I44_out, I49_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (A *> Z) = (0, 0);
     if (!C&D )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (B *> Z) = (0, 0);
     if (!C&D )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (D *> Z) = (0, 0);
     if (!A&B )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C&!D|A&!B&C&!D )
       (E *> Z) = (0, 0);
     if (A&!B&!C&D|!A&B&C&!D|!A&B&!C&D )
       (E *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI221HD2X (A, B, C, D, E, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
output Z ;

   and (I0_out, C, D);
   and (I1_out, A, B);
   or  (I2_out, I0_out, I1_out);
   or  (I3_out, I2_out, E);
   not (Z, I3_out);
   not (I5_out, C);
   not (I6_out, D);
   and (I7_out, I5_out, I6_out);
   not (I8_out, D);
   and (I9_out, C, I8_out);
   or  (\!C&!D|C&!D , I7_out, I9_out);
   not (I11_out, C);
   and (\!C&D , I11_out, D);
   not (I13_out, A);
   not (I14_out, B);
   and (I15_out, I13_out, I14_out);
   not (I16_out, B);
   and (I17_out, A, I16_out);
   or  (\!A&!B|A&!B , I15_out, I17_out);
   not (I19_out, A);
   and (\!A&B , I19_out, B);
   not (I21_out, A);
   not (I22_out, B);
   and (I23_out, I21_out, I22_out);
   not (I24_out, C);
   and (I25_out, I23_out, I24_out);
   not (I26_out, D);
   and (I27_out, I25_out, I26_out);
   not (I28_out, B);
   and (I29_out, A, I28_out);
   and (I30_out, I29_out, C);
   not (I31_out, D);
   and (I32_out, I30_out, I31_out);
   or  (\!A&!B&!C&!D|A&!B&C&!D , I27_out, I32_out);
   not (I34_out, B);
   and (I35_out, A, I34_out);
   not (I36_out, C);
   and (I37_out, I35_out, I36_out);
   and (I38_out, I37_out, D);
   not (I39_out, A);
   and (I40_out, I39_out, B);
   and (I41_out, I40_out, C);
   not (I42_out, D);
   and (I43_out, I41_out, I42_out);
   or  (I44_out, I38_out, I43_out);
   not (I45_out, A);
   and (I46_out, I45_out, B);
   not (I47_out, C);
   and (I48_out, I46_out, I47_out);
   and (I49_out, I48_out, D);
   or  (\A&!B&!C&D|!A&B&C&!D|!A&B&!C&D , I44_out, I49_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (A *> Z) = (0, 0);
     if (!C&D )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (B *> Z) = (0, 0);
     if (!C&D )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (D *> Z) = (0, 0);
     if (!A&B )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C&!D|A&!B&C&!D )
       (E *> Z) = (0, 0);
     if (A&!B&!C&D|!A&B&C&!D|!A&B&!C&D )
       (E *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module BUFHD12X (A, Z);
input  A ;
output Z ;

   buf (Z, A);

   specify
     // path delays
     (A *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI221HD4X (A, B, C, D, E, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
output Z ;

   and (I0_out, A, B);
   and (I1_out, C, D);
   or  (I2_out, I0_out, I1_out);
   or  (I3_out, I2_out, E);
   not (Z, I3_out);
   not (I5_out, C);
   not (I6_out, D);
   and (I7_out, I5_out, I6_out);
   not (I8_out, D);
   and (I9_out, C, I8_out);
   or  (\!C&!D|C&!D , I7_out, I9_out);
   not (I11_out, C);
   and (\!C&D , I11_out, D);
   not (I13_out, A);
   not (I14_out, B);
   and (I15_out, I13_out, I14_out);
   not (I16_out, B);
   and (I17_out, A, I16_out);
   or  (\!A&!B|A&!B , I15_out, I17_out);
   not (I19_out, A);
   and (\!A&B , I19_out, B);
   not (I21_out, A);
   not (I22_out, B);
   and (I23_out, I21_out, I22_out);
   not (I24_out, C);
   and (I25_out, I23_out, I24_out);
   not (I26_out, D);
   and (I27_out, I25_out, I26_out);
   not (I28_out, B);
   and (I29_out, A, I28_out);
   and (I30_out, I29_out, C);
   not (I31_out, D);
   and (I32_out, I30_out, I31_out);
   or  (\!A&!B&!C&!D|A&!B&C&!D , I27_out, I32_out);
   not (I34_out, B);
   and (I35_out, A, I34_out);
   not (I36_out, C);
   and (I37_out, I35_out, I36_out);
   and (I38_out, I37_out, D);
   not (I39_out, A);
   and (I40_out, I39_out, B);
   and (I41_out, I40_out, C);
   not (I42_out, D);
   and (I43_out, I41_out, I42_out);
   or  (I44_out, I38_out, I43_out);
   not (I45_out, A);
   and (I46_out, I45_out, B);
   not (I47_out, C);
   and (I48_out, I46_out, I47_out);
   and (I49_out, I48_out, D);
   or  (\A&!B&!C&D|!A&B&C&!D|!A&B&!C&D , I44_out, I49_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (A *> Z) = (0, 0);
     if (!C&D )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (B *> Z) = (0, 0);
     if (!C&D )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (D *> Z) = (0, 0);
     if (!A&B )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C&!D|A&!B&C&!D )
       (E *> Z) = (0, 0);
     if (A&!B&!C&D|!A&B&C&!D|!A&B&!C&D )
       (E *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI221HDLX (A, B, C, D, E, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
output Z ;

   and (I0_out, C, D);
   and (I1_out, A, B);
   or  (I2_out, I0_out, I1_out);
   or  (I3_out, I2_out, E);
   not (Z, I3_out);
   not (I5_out, C);
   not (I6_out, D);
   and (I7_out, I5_out, I6_out);
   not (I8_out, D);
   and (I9_out, C, I8_out);
   or  (\!C&!D|C&!D , I7_out, I9_out);
   not (I11_out, C);
   and (\!C&D , I11_out, D);
   not (I13_out, A);
   not (I14_out, B);
   and (I15_out, I13_out, I14_out);
   not (I16_out, B);
   and (I17_out, A, I16_out);
   or  (\!A&!B|A&!B , I15_out, I17_out);
   not (I19_out, A);
   and (\!A&B , I19_out, B);
   not (I21_out, A);
   not (I22_out, B);
   and (I23_out, I21_out, I22_out);
   not (I24_out, C);
   and (I25_out, I23_out, I24_out);
   not (I26_out, D);
   and (I27_out, I25_out, I26_out);
   not (I28_out, B);
   and (I29_out, A, I28_out);
   and (I30_out, I29_out, C);
   not (I31_out, D);
   and (I32_out, I30_out, I31_out);
   or  (\!A&!B&!C&!D|A&!B&C&!D , I27_out, I32_out);
   not (I34_out, B);
   and (I35_out, A, I34_out);
   not (I36_out, C);
   and (I37_out, I35_out, I36_out);
   and (I38_out, I37_out, D);
   not (I39_out, A);
   and (I40_out, I39_out, B);
   and (I41_out, I40_out, C);
   not (I42_out, D);
   and (I43_out, I41_out, I42_out);
   or  (I44_out, I38_out, I43_out);
   not (I45_out, A);
   and (I46_out, I45_out, B);
   not (I47_out, C);
   and (I48_out, I46_out, I47_out);
   and (I49_out, I48_out, D);
   or  (\A&!B&!C&D|!A&B&C&!D|!A&B&!C&D , I44_out, I49_out);

   specify
     // path delays
     ifnone (A *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (A *> Z) = (0, 0);
     if (!C&D )
       (A *> Z) = (0, 0);
     ifnone (B *> Z) = (0, 0);
     if (!C&!D|C&!D )
       (B *> Z) = (0, 0);
     if (!C&D )
       (B *> Z) = (0, 0);
     ifnone (C *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (C *> Z) = (0, 0);
     if (!A&B )
       (C *> Z) = (0, 0);
     ifnone (D *> Z) = (0, 0);
     if (!A&!B|A&!B )
       (D *> Z) = (0, 0);
     if (!A&B )
       (D *> Z) = (0, 0);
     ifnone (E *> Z) = (0, 0);
     if (!A&!B&!C&!D|A&!B&C&!D )
       (E *> Z) = (0, 0);
     if (A&!B&!C&D|!A&B&C&!D|!A&B&!C&D )
       (E *> Z) = (0, 0);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI222HD1X (A, B, C, D, E, F, Z);
input  A ;
input  B ;
input  C ;
input  D ;
input  E ;
input  F ;
output Z ;

   and (I0_out, E, F);
   and (I1_out, A, B);
   or  (I2_out, I0_out, I1_out);
   and (I3_out, C, D);
   or  (I4_out, I2_out, I3_out);
   not (Z, I4_out);
   not (I6_out, C);
   not (I7_out, D);
   and (I8_out, I6_out, I7_out);
   not (I9_out, E);
   and (I10_out, I8_out, I9_out);
   not (I11_out, F);
   and (I12_out, I10_out, I11_out);
   not (I13_out, D);
   and (I14_out, C, I13_out);
   and (I15_out, I14_out, E);
   not (I16_out, F);
   and (I17_out, I15_out, I16_out);
   or  (\!C&!D&!E&!F|C&!D&E&!F , I12_out, I17_out);
   not (I19_out, C);
   and (I20_out, I19_out, D);
   and (I21_out, I20_out, E);
   not (I22_out, F);
   and (I23_out, I21_out, I22_out);
   not (I24_out, D);
   and (I25_out, C, I24_out);
   not (I26_out, E);
   and (I27_out, I25_out, I26_out);
   and (I28_out, I27_out, F);
   or  (I29_out, I23_out, I28_out);
   not (I30_out, C);
   and (I31_out, I30_out, D);
   not (I32_out, E);
   and (I33_out, I31_out, I32_out);
   and (I34_out, I33_out, F);
   or  (\!C&D&E&!F|C&!D&!E&F|!C&D&!E&F , I29_out, I34_out);
   not (I36_out, A);
   not (I37_out, B);
   and (I38_out, I36_out, I37_out);
   not (I39_out, E);
   and (I40_out, I38_out, I39_out);
   not (I41_out, F);
   and (I42_out, I40_out, I41_out);
   not (I43_out, B);
   and (I44_out, A, I43_out);
   and (I45_out, I44_out, E);
   not (I46_out, F);
   and (I47_out, I45_out, I46_out);
   or  (\!A&!B&!E&!F|A&!B&E&!F , I42_out, I47_out);
   not (I49_out, A);
   and (I50_out, I49_out, B);
   and (I51_out, I50_out, E);
   not (I52_out, F);
   and (I53_out, I51_out, I52_out);
   not (I54_out, B);
   and (I55_out, A, I54_out);
   not (I56_out, E);
   and (I57_out, I55_out, I56_out);
   and (I58_out, I57_out, F);
   or  (I59_out, I53_out, I58_out);
   not (I60_out, A);
   and (I61_out, I60_out, B);
   not (I62_out, E);
   and (I63_out, I61_out, I62_out);
   and (I64_out, I63_out, F);
   or  (\!A&B&E&!F|A&!B&!E&F|!A&B&!E&F , I59_out, I64_out);
   not (I66_out, A);
   not (I67_out, B);
   and (I68_out, I66_out, I67_out);
   not (I69_out, C);
   and (I70_out, I68_out, I69_out);
   not (I71_out, D);
   and (I72_out, I70_out, I71_out);
   not (I73_out, B);