filter.v

插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现

            begin
              if(data_in)
                 begin 
                  data_out=data_in;
                  times=times+1;
                 end
            end     
         else
           begin
           data_out=0;
           times=times+1;
           if(times==3'b100)  
              times=0;
           end
      end

endmodule    

module minus(in1,in2,out);

input [19:1] in1,in2;
output [18:1] out;

reg [20:1] temp_in1,temp_in2;
reg [20:1] temp_out;
reg sign;
reg [18:1] out;

always@(in1 or in2)
  begin
    temp_in1={1'b0,in1};
    temp_in2=~{1'b0,in2}+1;
    temp_out=temp_in1+temp_in2;
    if(temp_out[20])
      begin
      temp_out=~temp_out+1;
      end
    else
    out=temp_out;
  end
endmodule    


module clk_divide(clock_in,reset,clock_hf,clock_lp,clock_sh);

input clock_in,reset;
output clock_hf,clock_lp,clock_sh;

reg clock_hf,clock_lp,clock_sh;
reg [4:0] cnt_hf;
reg [2:0] cnt_lp;


always@(posedge clock_in or negedge reset)
  if(!reset)
     begin
     clock_hf<=0;
     clock_lp<=1;
     clock_sh<=1;
     cnt_hf<=0;
     cnt_lp<=0;
     end
   else
     begin
     if(cnt_lp==7)
       begin
         clock_lp<=~clock_lp;
         cnt_lp<=0;
       end  
     else
       cnt_lp<=cnt_lp+1;  
     if(cnt_hf==31)
       begin
         clock_hf<=~clock_hf;
         cnt_hf<=0;
       end
     else    
       cnt_hf<=cnt_hf+1;
     clock_sh<=~clock_sh;       
     end             
endmodule


module mux_2(data_in1,data_in2,control,data_out);

input [18:1] data_in1,data_in2;
input control;
output [18:1] data_out;

assign data_out = control ? data_in1 : data_in2;

endmodule

module mux_4(data_in1,data_in2,data_in3,data_in4,control,data_out);

input [18:1] data_in1,data_in2,data_in3,data_in4;
input [2:1] control;
output [18:1] data_out;

reg [18:1] data_out;

always@(data_in1 or data_in2 or data_in3 or data_in4 or control)
case(control)
  2'b00 : data_out = data_in1;
  2'b01 : data_out = data_in2;
  2'b10 : data_out = data_in3;
  2'b11 : data_out = data_in4;
  default : data_out = 0;
endcase
endmodule  

module top_half(data_in,clock,reset,data_out);

input clock,reset;
input [18:1] data_in;
output [18:1] data_out;

wire [18:1] dwire,dwire1,dwire2,dwire3,dwire4,dwire5,dwire6,dwire7,dwire8,dwire9,dwire10;
wire [18:1] dwire11,dwire12,dwire13,dwire14,dwire15,dwire16,dwire17,dwire18,dwire19,dwire20;
wire [18:1] dwire21,dwire22,dwire23,dwire24,dwire25,dwire26,dwire27,dwire28,dwire29,dwire30;
wire [18:1] dwire31,dwire32,dwire33,dwire34,dwire35,dwire36,dwire37,dwire38,dwire39,dwire40;
wire [18:1] dwire41,dwire42,dwire43,dwire44,dwire45,dwire46;
wire [18:1] ffdwire;

wire [19:1] div_in1,div_in2,div_in3,div_in4,div_in5,div_in6,div_in7,div_in8,div_in9,div_in10,div_in11,div_in12,div_in13;
wire [18:1] div_out1,div_out2,div_out3,div_out4,div_out5,div_out6,div_out7,div_out8,div_out9,div_out10,div_out11,div_out12,div_out13;

wire [19:1] minus_in1,minus_in2;

assign div_in13={1'b0,dwire23};

FFD_hf_18 D(data_in,clock,reset,dwire);

FFD_hf_18 D1(dwire,clock,reset,dwire1),
          D2(dwire1,clock,reset,dwire2),
          D3(dwire2,clock,reset,dwire3),
          D4(dwire3,clock,reset,dwire4),
          D5(dwire4,clock,reset,dwire5),
          D6(dwire5,clock,reset,dwire6),
          D7(dwire6,clock,reset,dwire7),
          D8(dwire7,clock,reset,dwire8),
          D9(dwire8,clock,reset,dwire9),
          D10(dwire9,clock,reset,dwire10),
          D11(dwire10,clock,reset,dwire11),
          D12(dwire11,clock,reset,dwire12),
          D13(dwire12,clock,reset,dwire13),
          D14(dwire13,clock,reset,dwire14),
          D15(dwire14,clock,reset,dwire15),
          D16(dwire15,clock,reset,dwire16),
          D17(dwire16,clock,reset,dwire17),
          D18(dwire17,clock,reset,dwire18),
          D19(dwire18,clock,reset,dwire19),
          D20(dwire19,clock,reset,dwire20),
          D21(dwire20,clock,reset,dwire21),
          D22(dwire21,clock,reset,dwire22);
                   
FFD_hf_18   D23(dwire22,clock,reset,dwire23),
            D24(dwire23,clock,reset,dwire24);
                   
FFD_hf_18 D25(dwire24,clock,reset,dwire25),
          D26(dwire25,clock,reset,dwire26),
          D27(dwire26,clock,reset,dwire27),
          D28(dwire27,clock,reset,dwire28),
          D29(dwire28,clock,reset,dwire29),
          D30(dwire29,clock,reset,dwire30),
          D31(dwire30,clock,reset,dwire31),
          D32(dwire31,clock,reset,dwire32),
          D33(dwire32,clock,reset,dwire33),
          D34(dwire33,clock,reset,dwire34),
          D35(dwire34,clock,reset,dwire35),
          D36(dwire35,clock,reset,dwire36),
          D37(dwire36,clock,reset,dwire37),
          D38(dwire37,clock,reset,dwire38),
          D39(dwire38,clock,reset,dwire39),
          D40(dwire39,clock,reset,dwire40),
          D41(dwire40,clock,reset,dwire41),
          D42(dwire41,clock,reset,dwire42),
          D43(dwire42,clock,reset,dwire43),
          D44(dwire43,clock,reset,dwire44),
          D45(dwire44,clock,reset,dwire45),
          D46(dwire45,clock,reset,dwire46);
         
add_half    add1(dwire,dwire46,div_in1),
            add2(dwire2,dwire44,div_in2),
            add3(dwire4,dwire42,div_in3),
            add4(dwire6,dwire40,div_in4),
            add5(dwire8,dwire38,div_in5),
            add6(dwire10,dwire36,div_in6),
            add7(dwire12,dwire34,div_in7),
            add8(dwire14,dwire32,div_in8),
            add9(dwire16,dwire30,div_in9),
            add10(dwire18,dwire28,div_in10),
            add11(dwire20,dwire26,div_in11),
            add12(dwire22,dwire24,div_in12);
         
hf_division1  hf_division1(div_in1,clock,reset,div_out1);
hf_division2  hf_division2(div_in2,clock,reset,div_out2);
hf_division3  hf_division3(div_in3,clock,reset,div_out3);
hf_division4  hf_division4(div_in4,clock,reset,div_out4);
hf_division5  hf_division5(div_in5,clock,reset,div_out5);
hf_division6  hf_division6(div_in6,clock,reset,div_out6);
hf_division7  hf_division7(div_in7,clock,reset,div_out7);
hf_division8  hf_division8(div_in8,clock,reset,div_out8);
hf_division9  hf_division9(div_in9,clock,reset,div_out9);
hf_division10 hf_division10(div_in10,clock,reset,div_out10);
hf_division11 hf_division11(div_in11,clock,reset,div_out11);
hf_division12 hf_division12(div_in12,clock,reset,div_out12);
hf_division13 hf_division13(div_in13,clock,reset,div_out13);
         
add_plus add_plus(div_out2,div_out4,div_out6,div_out8,div_out10,div_out12,div_out13,minus_in1);

add_negative add_negative(div_out1,div_out3,div_out5,div_out7,div_out9,div_out11,minus_in2); 

minus minus(minus_in1,minus_in2,ffdwire);

FFD_hf_18 D48(ffdwire,clock,reset,data_out);

endmodule

module top_multi(data_in,clock,reset,data_out);

input [18:1] data_in;
input clock,reset;
output [18:1] data_out;

wire [18:1] dwire,dwire1,dwire2,dwire3,dwire4,dwire5,dwire6,dwire7,dwire8,dwire9,dwire10;
wire [18:1] dwire11,dwire12,dwire13,dwire14,dwire15,dwire16,dwire17,dwire18,dwire19,dwire20,dwire21;


wire [19:1] div_in1,div_in2,div_in3,div_in4,div_in5,div_in6,div_in7,div_in8,div_in9,div_in10,div_in11;
wire [18:1] div_out1,div_out2,div_out3,div_out4,div_out5,div_out6,div_out7,div_out8,div_out9,div_out10,div_out11;

wire [19:1] minus_in1,minus_in2;

wire [18:1] shift_in,shift_out;

assign div_in11={1'b0,dwire11};

FFD_lp_18 FFD(data_in,clock,reset,dwire);

upsample upsample(dwire,clock,reset,dwire1);

FFD_lp_18 FFD1(dwire1,clock,reset,dwire2),
          FFD2(dwire2,clock,reset,dwire3),
          FFD3(dwire3,clock,reset,dwire4),
          FFD4(dwire4,clock,reset,dwire5),
          FFD5(dwire5,clock,reset,dwire6),
          FFD6(dwire6,clock,reset,dwire7),
          FFD7(dwire7,clock,reset,dwire8),
          FFD8(dwire8,clock,reset,dwire9),
          FFD9(dwire9,clock,reset,dwire10),
          FFD10(dwire10,clock,reset,dwire11),
          FFD11(dwire11,clock,reset,dwire12),
          FFD12(dwire12,clock,reset,dwire13),
          FFD13(dwire13,clock,reset,dwire14),
          FFD14(dwire14,clock,reset,dwire15),
          FFD15(dwire15,clock,reset,dwire16),
          FFD16(dwire16,clock,reset,dwire17),
          FFD17(dwire17,clock,reset,dwire18),
          FFD18(dwire18,clock,reset,dwire19),
          FFD19(dwire19,clock,reset,dwire20),
          FFD20(dwire20,clock,reset,dwire21);
       
add_multi    add1(dwire1,dwire21,div_in1),
             add2(dwire2,dwire20,div_in2),
             add3(dwire3,dwire19,div_in3),
             add4(dwire4,dwire18,div_in4),
             add5(dwire5,dwire17,div_in5),
             add6(dwire6,dwire16,div_in6),
             add7(dwire7,dwire15,div_in7),
             add8(dwire8,dwire14,div_in8),
             add9(dwire9,dwire13,div_in9),
             add10(dwire10,dwire12,div_in10);
         
lp_division1 lp_division1(div_in1,clock,reset,div_out1);
lp_division2 lp_division2(div_in2,clock,reset,div_out2);
lp_division3 lp_division3(div_in3,clock,reset,div_out3);
lp_division4 lp_division4(div_in4,clock,reset,div_out4);
lp_division5 lp_division5(div_in5,clock,reset,div_out5);
lp_division6 lp_division6(div_in6,clock,reset,div_out6);
lp_division7 lp_division7(div_in7,clock,reset,div_out7);
lp_division8 lp_division8(div_in8,clock,reset,div_out8);
lp_division9 lp_division9(div_in9,clock,reset,div_out9);
lp_division10 lp_division10(div_in10,clock,reset,div_out10);
lp_division11 lp_division11(div_in11,clock,reset,div_out11);                

add_z add_z(div_out3,div_out4,div_out5,div_out9,div_out10,div_out11,minus_in1);

add_f add_f(div_out1,div_out2,div_out6,div_out7,div_out8,minus_in2); 

minus minus(minus_in1,minus_in2,shift_in);

shift_up shift_up(shift_in,shift_out);

FFD_lp_18 D21(shift_out,clock,reset,data_out);


endmodule

module top_sh(data_in,clock,reset,data_out);

input clock,reset;
input [18:1] data_in;
output [18:1] data_out;

reg [18:1] data_out;

always@(posedge clock or negedge reset)
  begin
    if(!reset)
       data_out=0;
    else
       data_out=data_in;
  end
endmodule

module top_core(data_in,clock,reset,control,data_out);

input [18:1] data_in;
input clock,reset;
input [4:1] control;
output [18:1] data_out;

wire [18:1] hf_out,multi_out,sh_out,mux1_out,mux2_out;
wire clock_hf,clock_lp,clock_sh;

clk_divide clk_divide(clock,reset,clock_hf,clock_lp,clock_sh);
top_half top_half(data_in,clock_hf,reset,hf_out);
mux_2 mux1(hf_out,data_in,control[1],mux1_out);
top_multi top_multi(mux1_out,clock_lp,reset,multi_out);
mux_2 mux2(multi_out,data_in,control[2],mux2_out);
top_sh top_sh(mux2_out,clock_sh,reset,sh_out);
mux_4 mux3(data_in,mux1_out,mux2_out,sh_out,control[4:3],data_out);


endmodule

module iopads(clock_in_pad,reset_pad,control_pad,data_in_pad,data_out_core,clock_in_core,reset_core,control_core,data_in_core,data_out_pad);

input clock_in_pad,reset_pad;
input [4:1] control_pad;
input [18:1] data_in_pad,data_out_core;
output clock_in_core,reset_core;
output [4:1] control_core;
output [18:1] data_in_core,data_out_pad;

//PLVDDC vdd_core_block (  );
//PLVSSC gnd_core_block (  );

//PLVDDH vdd_pad_block (  );
//PLVSSH gnd_pad_block (  );

//PLVDDO vdd_osc_block (  );
//PLVSSO gnd_osc_block (  );

PSOSC14M clock_block(.CK(clock_in_core),.XTALOUT(),.EI(1'b1),.EO(1'b0),.XTALIN(clock_in_pad));

PLBI16N reset_block(.D(reset_core), .P(reset_pad), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b1));

PLBI16N control_block1(.D(control_core[1]), .P(control_pad[1]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b1));
PLBI16N control_block2(.D(control_core[2]), .P(control_pad[2]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b1));
PLBI16N control_block3(.D(control_core[3]), .P(control_pad[3]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b1));
PLBI16N control_block4(.D(control_core[4]), .P(control_pad[4]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b1));

PLBI8N data_in_block1(.D(data_in_core[1]), .P(data_in_pad[1]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block2(.D(data_in_core[2]), .P(data_in_pad[2]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block3(.D(data_in_core[3]), .P(data_in_pad[3]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block4(.D(data_in_core[4]), .P(data_in_pad[4]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block5(.D(data_in_core[5]), .P(data_in_pad[5]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block6(.D(data_in_core[6]), .P(data_in_pad[6]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block7(.D(data_in_core[7]), .P(data_in_pad[7]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block8(.D(data_in_core[8]), .P(data_in_pad[8]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block9(.D(data_in_core[9]), .P(data_in_pad[9]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block10(.D(data_in_core[10]), .P(data_in_pad[10]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block11(.D(data_in_core[11]), .P(data_in_pad[11]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block12(.D(data_in_core[12]), .P(data_in_pad[12]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block13(.D(data_in_core[13]), .P(data_in_pad[13]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block14(.D(data_in_core[14]), .P(data_in_pad[14]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block15(.D(data_in_core[15]), .P(data_in_pad[15]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block16(.D(data_in_core[16]), .P(data_in_pad[16]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block17(.D(data_in_core[17]), .P(data_in_pad[17]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_in_block18(.D(data_in_core[18]), .P(data_in_pad[18]), .A(1'b0), .CONOF(1'b1), .NEN(1'b0), .PD(1'b0), .PEN(1'b0), .PU(1'b1), .SONOF(1'b0));


PLBI8N data_out_block1(.D(), .P(data_out_pad[1]), .A(data_out_core[1]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block2(.D(), .P(data_out_pad[2]), .A(data_out_core[2]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block3(.D(), .P(data_out_pad[3]), .A(data_out_core[3]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block4(.D(), .P(data_out_pad[4]), .A(data_out_core[4]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block5(.D(), .P(data_out_pad[5]), .A(data_out_core[5]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block6(.D(), .P(data_out_pad[6]), .A(data_out_core[6]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block7(.D(), .P(data_out_pad[7]), .A(data_out_core[7]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block8(.D(), .P(data_out_pad[8]), .A(data_out_core[8]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block9(.D(), .P(data_out_pad[9]), .A(data_out_core[9]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block10(.D(), .P(data_out_pad[10]), .A(data_out_core[10]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block11(.D(), .P(data_out_pad[11]), .A(data_out_core[11]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block12(.D(), .P(data_out_pad[12]), .A(data_out_core[12]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block13(.D(), .P(data_out_pad[13]), .A(data_out_core[13]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block14(.D(), .P(data_out_pad[14]), .A(data_out_core[14]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block15(.D(), .P(data_out_pad[15]), .A(data_out_core[15]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block16(.D(), .P(data_out_pad[16]), .A(data_out_core[16]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block17(.D(), .P(data_out_pad[17]), .A(data_out_core[17]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));
PLBI8N data_out_block18(.D(), .P(data_out_pad[18]), .A(data_out_core[18]), .CONOF(1'b0), .NEN(1'b1), .PD(1'b0), .PEN(1'b1), .PU(1'b1), .SONOF(1'b0));

endmodule

module filter(data_in,clock,reset,control,data_out);

input [18:1] data_in;
input clock,reset;
input [4:1] control;
output [18:1] data_out;

wire [18:1] data_in_core,data_out_core;
wire [4:1] control_core;
wire clock_core,reset_core;

top_core top_core(data_in_core,clock_core,reset_core,control_core,data_out_core);
iopads iopads(clock,reset,control,data_in,data_out_core,clock_core,reset_core,control_core,data_in_core,data_out);

endmodule