filter.v

插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现

        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>4)+(temp_data>>9)+(temp_data>>10)+(temp_data>>12)+(temp_data>>14)+(temp_data>>18)+{~(temp_data>>7)+1};
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule          

module hf_division11(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>4)+(temp_data>>5)+(temp_data>>7)+(temp_data>>10)+(temp_data>>15)+(temp_data>>18);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule          

module hf_division12(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>2)+(temp_data>>4)+(temp_data>>8)+(temp_data>>11)+(temp_data>>12)+(temp_data>>17)+(temp_data>>18)+{~(temp_data>>15)+1};
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule        

module hf_division13(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        data_out=0;
     else
       if(data_in[1]==1)
          data_out=(data_in+1)>>1;
       else
          data_out=data_in>>1;
   end
endmodule        

module lp_division1(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>8)+(temp_data>>9)+(temp_data>>12)+(temp_data>>14)+(temp_data>>15)+(~(temp_data>>18)+1);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule         

module lp_division2(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>9)+(temp_data>>11)+(temp_data>>13)+(temp_data>>14)+(~(temp_data>>18)+1);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule           

module lp_division3(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>7)+(temp_data>>9)+(temp_data>>11)+(temp_data>>16);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule    

module lp_division4(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>6)+(temp_data>>8)+(temp_data>>10)+(temp_data>>13)+(temp_data>>16)+(temp_data>>18);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule           

module lp_division5(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>8)+(temp_data>>9)+(temp_data>>13)+(temp_data>>15)+(temp_data>>16)+(temp_data>>18);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule          

module lp_division6(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>5)+(temp_data>>9)+(temp_data>>10)+(temp_data>>15)+(~(temp_data>>14)+1)+(~(temp_data>>18)+1);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule          

module lp_division7(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>4)+(temp_data>>9)+(temp_data>>10)+(temp_data>>12)+(temp_data>>14)+(temp_data>>15)+(~(temp_data>>7)+1);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule           

module lp_division8(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>7)+(temp_data>>11)+(~(temp_data>>16)+1);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule         

module lp_division9(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>3)+(temp_data>>10)+(temp_data>>13)+(temp_data>>14)+(~(temp_data>>18)+1);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule           

module lp_division10(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>2)+(temp_data>>6)+(temp_data>>7)+(temp_data>>9)+(temp_data>>10)+(temp_data>>14)+(temp_data>>16);
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule           

module lp_division11(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [38:1] temp_data;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        begin
          data_out=0;
          temp_data=0;
        end  
     else
        begin
          temp_data={data_in,19'b0000000000000000000};
          temp_data=(temp_data>>2)+(temp_data>>4)+(temp_data>>5)+(temp_data>>8)+(temp_data>>13)+(temp_data>>14)+(temp_data>>17)+(temp_data>>18)+{~(temp_data>>11)+1};
          if(temp_data[19]==1)
             data_out=temp_data[37:20]+1;
          else
             data_out=temp_data[37:20];   
         end    
   end 
endmodule           

module shift_up(data_in,data_out);

input [18:1] data_in;
output [18:1] data_out;

assign data_out=data_in<<2;

endmodule

module upsample(data_in,clock,reset,data_out);

input [18:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;
reg [3:1] times;

always@(posedge clock or negedge reset)
    if(!reset)
       begin
         data_out=0;
         times=0;
       end
    else 
      begin
         if(!times)