clock_divide.v

来自「插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现」· Verilog 代码 · 共 46 行

module clk_divide(clock_in,reset,clock_hf_1,clock_hf_2,clock_lp,clock_sh);

input clock_in,reset;
output clock_hf_1,clock_hf_2,clock_lp,clock_sh;

reg clock_hf_1,clock_hf_2,clock_lp,clock_sh;
reg [3:0] cnt_hf;
reg [1:0] cnt_lp;
reg clock_sh1,clock_sh2,clock_sh3;
reg clock_lp1;


always@(posedge clock_in or negedge reset)
  if(!reset)
     begin
     clock_hf_1<=0;
     clock_hf_2<=0;
     clock_lp<=1;
     clock_sh<=0;
     cnt_hf<=0;
     cnt_lp<=0;
     end
   else
     begin
     if(cnt_lp==3)
       begin
         clock_lp1<=~(clock_lp1);
         clock_lp<=clock_lp;
         cnt_lp<=0;
       end  
     else
       cnt_lp<=cnt_lp+1;  
     if(cnt_hf==15)
       begin
         clock_hf_1<=~clock_hf_1;
         clock_hf_2<=~clock_hf_2;
         cnt_hf<=0;
       end
     else    
       cnt_hf<=cnt_hf+1;   
     clock_sh1<=clock_in;
     clock_sh2<=clock_sh1;
     clock_sh3<=clock_sh2;
     clock_sh<=clock_sh3; 
     end             
endmodule